Switching circuit artifact

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I have a simple switching circuit intended to swap a pair of 5 volt pulsed signals (PPM) between two destinations. Both signals are 60 Hz, but with different pulse widths. A schematic is attached. The switching is driven by an AVR output pin driving the gate of an NFET(Q1). The drain of the NFET drives the gate of a PFET(Q4) which switches ON/OFF one of the pulsed signals. The other pulsed signal is switched ON/OFF by a second PFET(Q5) driven by the same AVR output pin.

The circuit is intended to swap the signals headed to the ICP1 input on the AVR when it sends the output pin high.

 

On the attached scope images, the yellow trace is looking at the output drain of Q5 (channel A on the schematic) and the blue trace is looking at the output drain of Q4 (channel B).

 

When the AVR switch signal is high, Q5 shuts off and Q4 turns on, presenting the Channel B signal to ICP1, as it should. The channel A signal is OFF.

The problem occurs when the AVR switch signal is low. Then, Q1 is OFF, and Q4 should be OFF. Q5 is ON and the channel A pulse is presented to ICP1. But as you can see, an artifact of the Channel B pulse seems to leak through Q4, and both signals end up on ICP1.

 

I don't know why this is happening, and I wonder whether any of you might.

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You’ve not shown us the complete circuit, so I’ll take a guess. The waveform looks differentiated, so there’s some capacitance at play. Maybe you need a pullup/pulldown resistor on icp1 to swamp some parasitic capacitances of the mosfets.
If you want a multiplexer, why not just use a 4051?

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Oh, because I didn't think of that, I guess. It does look like the 4051 would do the job.

I got wound up with trying to do it this way, and now I am trying to understand why this works the way it does.

A 10K pull down on drain of Q4 does solve the problem, so thanks for that suggestion. I'm still wondering about the mosfet capacitance though. Is it the gate capacitance in Q4?

Assume that the rest of the circuit not shown is just a load resistor.

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You circuit is "junk", the diodes in the fet will cause a backflow problem.  you should always include the diodes on the schematic for clarity.

 

Whatever is on ICP1 will be forced to appear on both CHA & CHB, wherever it comes from.  At that point, it becomes arm wrestling, the stronger wins. ChanB  might be strong and unmovable

by a weaker A (goodbye burned up diode).

 

Note you can also get funny waves when your probe is slid to the ac coupling mode (some probes have that option), even if the scope is set to DC coupling...seen that happen too.

 

Use a GATE (preferred), not an analog 4051...don't you want a logic signal going to ICP1?  Get one with a Schmitt trigger input for maximum happiness.

 

 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Fri. Jul 13, 2018 - 11:17 PM
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I do want the 5v logic signal that is on either A or B (not both) to get to ICP1.

Wouldn't a diode on the drains of Q4 qnd Q5 solve the backflow problem?

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Did you look at the diodes I  mentioned?  Use the datasheet & Include them in your schematic! Whatever signal appears on ICP1 will also be on BOTH A & B due to the diodes.

 

Wouldn't a diode on the drains of Q4 qnd Q5 solve the backflow problem?

Yes, only diodes in the fwd direction from A & B (but with more diode drop)...forget all the parts, just wire up a simple gate.

 

for a real solution, try

NC7SZ157P6X  mux chip

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Sat. Jul 14, 2018 - 01:31 AM
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Yes, I agree that a logic IC is the best way to do this. Thanks for the comments.