Is timed sequence needed when changing WDT prescaler?

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Hi,

until today I have believed changing Watchdog prescaler in AVRs need the timed sequence - setting WDE and WDCE and in 4 clock cycles change the prescaler. But I did not use it today on ATTiny85 by mistake and it worked anyway! So I started looking for information. My ATTiny25/45/85 Datasheet says the WDT have 2 safety levels: when WDTON fuse is not programmed, timed sequence is needed for clearing WDE bit only. When WDTON fuse is programmed, timed sequence is needed for changing prescaler and changing WDE is impossible. The same information is i.e. in ATTiny2313 Datasheet but most other AVRs have this formulation:

The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System
Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt
mode bit (WDTIE) are locked to 1 and 0 respectively. To further ensure program security, alterations
to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and
changing time-out configuration is as follows: (...)

But otherwise the WDT looks very similar. In AVR132 appnote in section 2.5 they say:

If the WDTON fuse is unprogrammed on ATtiny13 and ATtiny2313, it is possible to

change the WDT timeout period without following the timed sequence.

But both ATTiny13 and ATTiny13A have the more common formulation quoted above. So - are there 2 very similar versions of WDT in AVR devices or is the timed sequence not needed when changing prescaler with WDTON unprogrammed?

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Watchdog operation may be different from model to model, let the DS be your guide.

 

Jim

 

 

(Possum Lodge oath) Quando omni flunkus, moritati.

"I thought growing old would take longer"

 

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It can be confusing.  Mega88-family datasheet

To further ensure program security, alterations to the Watchdog set-up must follow timed
sequences. The sequence for clearing WDE and changing time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic
one must be written to WDE regardless of the previous value of the WDE bit.
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with
the WDCE bit cleared. This must be done in one operation.
 

...but it isn't entirely clear if this only applies to the previous mention of WDTON or not.

 

I remember having to fuss with order of operations when interrupt mode just came out.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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When I got home I tried ATMega328p (Arduino). It truly needs timed sequence to change prescaler but for enabling/disabling the interrupt timed sequence is not needed. So the WDTs are slightly different. As a byproduct I have found interesting behavior: disabling interrupt (clearing WDIE) also clears the interrupt flag regardless if the WDIF bit is written 0 or 1. When WDIE is set again the WDIF stays cleared. At least ATMega works this way...

 

EDIT: I finally found time to test the ATTiny13A. Despite what the Datasheet says it IS POSSIBLE to change WDT prescaler of ATTiny13A without following the timed sequence when WDON fuse is unprogrammed!

Last Edited: Wed. Jul 18, 2018 - 03:50 PM