SAM E70: problem with SDRAM on high frequencies

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#1
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Hello,

 

We designed a custom board similar to ATSAME70-XPLD with ATSAME70Q21A microcontroller. There is also SDRAM chip IS42S16800F-5TLI there.

 

The problem is that SDRAM doesn't work when I set Fmck higher than 180 MHz. while the SDRAM on the ATSAME70-XPLD board works perfectly with the frequency 300 MHz.

 

What can be the reason of it? Is it a hardware issue (like bad layout, unmatched lines etc.) or a software one (wrong configuration)?

 

Kind regards,

Sergey

 

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if you are running similar software on both, then it would narrow things down.  Signal integrity (line impedance, cross-talk, and terminations) are the most likely issue though.

jeff

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Hello Jeff,

 

Thank you for your reply. We will pay more attention to the routing then and redesign the board.

 

Kind regards,

Sergey

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depending on the tools available, you may want to do further tests on this board before you respin.  If you do not have terminations, even white wired ones should improve things (although the quality of the white wire will be an issue).

jeff

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Check the data sheet on your memory device IS42S16800F-5TLI - it's rated to 200MHz only

 

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/* SDRAM MT48LC16M16A2 configuration */

const sdramc_memory_dev_t SDRAM_MICRON_MT48LC16M16A2 = {

24, /* Block1 is at the bit 25, 2+9+13+1. */

0, // Set SDRAMC to normal mode, CAS = 3 (this was incorrectly set to 0)

/*

     * This configures the SDRAM with the following parameters in the

     *mode register:

     * - bits 0 to 2: burst length: 1 (000b);

     * - bit 3: burst type: sequential (0b);

     * - bits 4 to 6: CAS latency;

     * - bits 7 to 8: operating mode: standard operation (00b);

     * - bit 9: write burst mode: programmed burst length (0b);

     * - all other bits: reserved: 0b.

     */

{

SDRAMC_CR_NC_COL9      | /* 9 column bits. */

SDRAMC_CR_NR_ROW13     | /* 13 row bits    (2K). */

SDRAMC_CR_NB_BANK4     | /* SDRAM 4 bank. */

SDRAMC_CR_CAS_LATENCY3 | /* CAS Latency 3. */

SDRAMC_CR_DBW          | /* Data bus width 16 bits. */

SDRAMC_CR_TWR(2)       | /* Write Recovery Delay. */ //14ns

SDRAMC_CR_TRC_TRFC(9)  | /* Row Cycle Delay and Row Refresh Cycle. */ //63ns

SDRAMC_CR_TRP(3)       | /* Row Precharge Delay. */ //21ns

SDRAMC_CR_TRCD(3)      | /* Row to Column Delay. */ //21ns

SDRAMC_CR_TRAS(6)      | /* Active to Precharge Delay. */ //42ns

SDRAMC_CR_TXSR(10)       /* Exit from Self Refresh to Active Delay. */ //70ns

},

};