SAMD21, generic clocks for TC in 32b mode

Go To Last Post
2 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Hi,

I am confused by information from datasheet:

 

15.8.3 Generic Clock Control / register CLKCTRL / Bits 5:0 – ID[5:0]: Generic Clock Selection ID

Table 15-5 page 119:

 

0x1A ... GCLK_TCC0, GCLK_TCC1 ... TCC0,TCC1
0x1B ... GCLK_TCC2, GCLK_TC3 ..... TCC2,TC3
0x1C ... GCLK_TC4, GCLK_TC5 ....... TC4,TC5

0x1D ... GCLK_TC6, GCLK_TC7 ....... TC6,TC7

 

From this table it looks like TC pairs that share the same generic clock are for example TC4+TC5 or TC6+TC7

 

 

30. TC – Timer/Counter

30.5.3 Clocks, page 535:

....
The different TC instances are paired, even and odd, starting from TC3, and use the same generic clock,
GCLK_TCx. This means that the TC instances in a TC pair cannot be set up to use different GCLK_TCx
clocks.

 

30.6.2.4 Counter Mode, page 538:

....

• COUNT32: This mode is achieved by pairing two 16-bit TC peripherals. TC3 is paired with TC4,
and TC5 is paired with TC6. TC7 does not support 32-bit resolution.
When paired, the TC peripherals are configured using the registers of the even-numbered TC (TC4 or
TC6 respectively). The odd-numbered partner (TC3 or TC5 respectively) will act as slave, and the Slave
bit in the Status register (STATUS.SLAVE) will be set. The register values of a slave will not reflect the
registers of the 32-bit counter. Writing to any of the slave registers will not affect the 32-bit counter.
Normal access to the slave COUNT and CCx registers is not allowed.

 

From this description it looks like TC pairs for 32b mode are TC3+TC4 and TC5+TC6,

but it doesn't match the info that pairs TC4+TC5 and TC6+TC7 share the same generic clock.

So, which part of datasheet is wrong ?

 

Or is it necessary, in order to make 32b timer TC5+TC6,

to configure generic clock for TC4+TC5  == the same as generic clock for TC6+TC7 ?

(=> 4 timers TC4,TC5,TC6,TC7 must have the same clocks just to create one 32b timer)

 

Last Edited: Tue. Jun 19, 2018 - 08:23 AM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

One even TC and the following odd are a pair as I recall and that is what it looks like in the ASF-3 implementation (TC4 master and TC5 the slave for example).

Note the pairing is different for SAMD09, SAMD10, SAMD11 and SAMHA1 (might have caused the datasheet confusion).

 

#if SAMD09 || SAMD10 || SAMD11 || SAMHA1
    /* Check if even numbered TC modules are being configured in 32-bit
     * counter size. Only odd numbered counters are allowed to be
     * configured in 32-bit counter size.
     */
    if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
            !((instance + TC_INSTANCE_OFFSET) & 0x01)) {
        Assert(false);
        return STATUS_ERR_INVALID_ARG;
    }
#else
    /* Check if odd numbered TC modules are being configured in 32-bit
     * counter size. Only even numbered counters are allowed to be
     * configured in 32-bit counter size.
     */
    if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
            ((instance + TC_INSTANCE_OFFSET) & 0x01)) {
        Assert(false);
        return STATUS_ERR_INVALID_ARG;
    }
#endif

/Lars