AVR Freaks

Caveat: know (almost) nothing about SAM R21. But, I wonder...

Are the "complementary" pins on the same port? If not, there won't there be a delay between the two pin changes, depending on the clock rate?

Jim

This spikes may be significant w.r.t. absolute maximums, but I'd characterise them as minimal for an open-circuit piezo.  Naturally, since your two drive pins are low-impedance.

I've nowhere near the experience of other respondents.  However, when I've fiddled with direct drive of piezos and small magnet+coil speakers in the past, I found that I had to keep the output drive enabled until the transducer had settled down.  While prototyping I mistakenly configured the two complementary drive pins as inputs when placing the unit into a sleep mode.  Whenever this happened, the unit would latch up or otherwise malfunction.  A bit of poking around with a scope and I discovered that doing so immediately after playing a sample would result in very high voltages appearing across the two drive pins, as the transducer returned to a neutral position, rebounding a few times on the way.  In retrospect, this was obvious since as inputs they go high-impedance.

Keeping the drive pins as outputs even in sleep, or at least for a few hundred ms after a sample was played, would prevent this.  While the pins did still experience slight over- and under-voltages, this was a one-off and I wans't concerned.  The unit is still in service today, some 5 years later.  I have not, however, characterised it's low-power performance after that length of time in service.

So the moral/question is, does one or both of your two piezo drive pins ever go high-impedance?  If so, can it happen immediately after a tone is played?  If so, then much higher voltages than you have seen during drive, and captured above, may be hitting those pins, and that could indeed cause problems down the road.

Or, as suggested, the SAM might be more sensitive to over-voltages in I/O pins, and even the slight over-voltage you've seen might be enough to explain your symptoms.

How much over voltage does it take to induce CMOS latch-up?  Latch-up will certainly increase current draw but 1 mA seems low for that scenario.

What happens to Vcc during those spikes? If the answer is nothing, then, as Paul alludes, maybe the top-side protection diodes are gone.

Jim

Why do you think it is the piezo...could it be some other circuitry?  What happens if you remove the piezo? 

An IO pin that should be an input that gets set as an output could cause contention(current). 

How do you measure the current? As always, is there a schematic?

That was were I was going next, but West Coast Jim beat me to it!

5v, M48's mostly, no experience with SAM parts, but you were just investigating and wondered if this may be the cause.

You could try placing a resistor in series with one or both legs and see if it helps. 

My guess is its not related, I'd look for a bug in the code that is preventing the mpu from achieving as deep a sleep mode as intended.

Does a failed unit always draw more current, have you tested a failed unit with a simple sleep mode current test?

Good luck with the troubleshooting.

Jim

NXP AN2434, even if about another uC family, has some good info on ESD diodes.

[should have read all the answers before commenting, but still believe this is the root cause.  Series R will limit current into the diodes, but a shunt path will reduce voltage spikes. I assumed that you were seeing the spike at the end of a toggle sequence, but even in a constant drive mode, the CMOS pair are a break before make switch (or there would be momentary Vdd to Vss short).  You have an open circuit resonator on every cross-over, IMHO.]

Andy,

The piezoelectric element resonates.  If you drive it with a voltage it produces motion, but the motion continues after the drive signal and motion moves charge.  (Piezen - to squeeze --> electricity).

With the driver off, the impedance is probably high, so the charge is running into the ESD clamps.  Eventually the ESD diodes leak.

If you can afford a little more drive current, a shunt resistor will reduce the voltage that the piezo pushes back. 

Alternately, a bidirectional TVS across the piez0.