I'm trying to interface mega64 with external ram but there is some strange behavior when debugging it.
I'm using 74AHC573 as D latch and IS61LV256 as external ram. The linker options that I'm using in Atmel Studio is:
The memory initialization is done in .init3 section so it should be up and running before any variable initialization. I'm using short program from https://scienceprog.com/adding-external-memory-to-atmega128/ to test the XRAM.
The problem that I'm having is when the program is populating the memory it always stores same data in two addresses (duplicating the data) but can't figure what could be causing it. Data array starts at beginning of XRAM (0x1100).
I was suspecting on timing constrains but they are generally focused on D-latch chip as stated in mega64 datasheet:
However, most latches can be used as long they comply with the main timing parameters. The main parameters for the address latch are:
- D to Q propagation delay (tpd).
- Data setup time before G low (tsu).
- Data (address) hold time after G low (th).
Anybody has any idea what could be causing this behavior ?