ATxmega128A1U - ADC & DMA Redux

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Hello All,

 

I am trying to get all four channels from a free-running ADCA transferred into an 8-byte RAM buffer.  The concept is that the RAM buffer will contain the latest ADC values at any given point in time, which will be read via an SPI transfer (DMA - RAM to SPI).

The ADC appears to be working fine.  I can stream all four values out over a serial port, and the data looks as it should.  The DMA RAM-to-SPI works great.  However, getting the DMA to transfer ADC conversion results to RAM is not so good.

 

For testing, I am using a command that sets the TRFREQ bit in the DMA_CH2_CTRLA register.

Source address is ADCA_CH0_RES, increment

Destination address is (RAM), increment

block size is 8

I am not clear what do with BURSTLEN, REPEAT, SINGLE-SHOT, etc., when using the ADC as the source.

 

I ran a test where I replaced the source address with another location in RAM, and the DMA transferred the 8 bytes from one section of RAM to another, just fine.

 

Can someone who has done this before give me a hint?  I have searched the forum, and haven't quite found anything that covers this.

 

Thanks in advance.

 

Altazi

 

EDIT: I do know that the ADC result registers are 16-bit, so the BURSTLEN should be at least two bytes in length to avoid data skew or other disturbance.  Where I am uncertain is should BURSTLEN be two bytes, and the DMA controller somehow transfers one channel result at a time, or should BURSTLEN be eight bytes, and transfer all of the ADC results at once.  I would appreciate hearing from anyone who has gotten this working.

 

I have reviewed the APP note 1304, and it helped some - with the RAM-to-SPI transfer.

 

Thanks in advance.

 

Altazi

Last Edited: Tue. Feb 20, 2018 - 07:27 AM
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Thank you.

 

I resolved the problem after realizing that there were two sets of ADC conversion results registers.

 

I was first using the channel registers, ADCA_CHn_RES (L & H), whose addresses are not in a linear sequence - e.g., ADCA_CH0_RESL at ADCA + $24, ADCA_CH1_RESL at ADCA + $34, etc.  This resulted in the channel 0 results being transferred properly, but the rest of the transfer wasn't channels 1-3.

 

The trick is to use the ADCA channel registers, ADCA_CH0RES - ADCA_CH3RES, whose addresses are in a contiguous linear sequence from ADCA + $10 through ADCA + $17.

 

Sigh.