How to figure out where GCLK_GENERATOR_2 got initialized in ASF example

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Hi all,

I am walking through the ASF example for SAMD_QTOUCH_SELFCAP_EXMPLE1, everything is working fine, and the frequency is also checked out, but I can't figure out the way the ASF example source code showing


To be specific, the example has the defines for the GCLK generator 2 (RTC) is disable, only GENERATOR_0 and GENERATOR_1 are enable


/* Set this to true to configure the GCLK when running clocks_init. If set to
 * false, none of the GCLK generators will be configured in clocks_init(). */
#  define CONF_CLOCK_CONFIGURE_GCLK               true

/* Configure GCLK generator 0 (Main Clock) */
#  define CONF_CLOCK_GCLK_0_ENABLE                true
#  define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY        false
#  define CONF_CLOCK_GCLK_0_PRESCALER             2
#  define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE         false

/* Configure GCLK generator 1 */
#  define CONF_CLOCK_GCLK_1_ENABLE                true
#  define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY        false
#  define CONF_CLOCK_GCLK_1_PRESCALER             2
#  define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE         false

/* Configure GCLK generator 2 (RTC) */
#  define CONF_CLOCK_GCLK_2_ENABLE                false
#  define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY        false
#  define CONF_CLOCK_GCLK_2_PRESCALER             32
#  define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE         false



But when the rtc_count_init() was call the GCLK_GENERATOR_2 got referenced


enum status_code rtc_count_init(

              struct rtc_module *const module,

              Rtc *const hw,

              const struct rtc_count_config *const config)


       gclk_chan_conf.source_generator = GCLK_GENERATOR_2;

       system_gclk_chan_set_config(RTC_GCLK_ID, &gclk_chan_conf);




And they use 33 to represent for 1ms which indicate the RTC_GCLK is around 33KHz or the closest clock is 32.768KHz

 * RTC Interrupt timing definition
#define TIME_PERIOD_1MSEC 33u


This is the part I couldn't figure out how GENERATOR_2 got initialized.


Thank you for your time.

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Thank  you guys,

I found the information for the clocks are configured as mentioned in section "Clocks after Reset" in "Clock System" section of device datasheet. 

"All generic clock generators disabled except: 
- the generator 0 (GCLK_MAIN) using OSC8M as source, with no division 
- the generator 2 using OSCULP32K as source, with no division"