No contiguous clock when using SPI over USART

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I intend to use SPI over USART to drive the BiSS protocol of a sensor.

I configured USART as SPI master with 8 bit, CPHA=1 and CPOL=1. When sending data I check for TXRDY (not TXEMPTY). What I expect is a contigous clock with at contigous data stream when sending my bytes.

But no matter which USART clock I try I always get a gap of 3.5 clock cycles between the 8-bit-clock-sequences. This causes the BiSS protocol to fail.

 

I need help to figure out how I can get rid of that clock gap.

Last Edited: Tue. Dec 12, 2017 - 11:03 AM
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We will need some help too, please show a small complete program that demo's the problem along with a Logic Analyzer output showing the issue.

 

 

Jim

 

Mission: Improving the readiness of hams world wide : flinthillsradioinc.com

Interests: Ham Radio, Solar power, futures & currency trading - whats yours?

 

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beteso wrote:
BiSS protocol

You mean this: https://en.wikipedia.org/wiki/BiSS_interface ?

 

You haven't said what chip you're using.

 

Does it have double-buffering for transmit, which might avoid this gap ... ?

 

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It is an ******** undesired side-effect of using the USART hardware to do SPI.
The datasheet says "A delay for at least three bit periods is always inserted in between characters".

*If* you can, use the 'real' SPI module(s).

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Can you use ordinary SPI?  The SPI interface on the Mega AVRs can be set to 1/4 of system clock speed, and possibly slower.  SPI's data register can be loaded with a value which will start the 8-pulse interface process.  The CPU then has about 24 or so clocks to set up the next byte to be sent before the SPI generates an interrupt when the transmission completes.  In this manner, a 16MHz system will send bursts of data with bytes being output every two microseconds without gaps between each byte.

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Simonetta wrote:
on the Mega AVRs 

Note that we are in the UC3 (AVR32) forum

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Thanks for your comments and sorry for not being precise enough: I'm using USART4 module of an AT32UC3C0512C. And yes it's that BiSS you found on wikipedia. (But this doesn't really matter for the question. It's just background information about my motivation.)

 

mikech thanks for your hint.  The datasheet of the current ATUC3C says the same in other words:

"In SPI Master Mode, the slave select line (NSS) is asserted at low level 1 Tbit before the trans-
mission of the MSB bit and released at high level 1 Tbit after the transmission of the LSB bit. So,
the slave select line (NSS) is always released between each character transmission and a mini-
mum delay of 3 Tbits always inserted
."

 

That's exactly what I can watch on my oscilloscope.

 

I tried to force NSS via setting RTSEN to 1 but this has no effect on clock timing.

 

I'm afraid I have to give up the approach to drive SPI (BiSS) over USART. Unfortunately both SPI modules are already in use.

 

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Bit-banging it is, then ...

Top Tips:

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  3. Wrong baud rate is usually due to not running at the speed you thought; check by blinking a LED to see if you get the speed you expected
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