Closed loop DFLL48M w/START for SAMD20

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I'm trying to make a configuration of closed loop DFLL48M with the Atmel START with no success. 

can someone give me the exact configuration in every cell of the clock configuration in the START (clocks, gclk, cpu), I want to use the internal 32k oscillator if possible.

It seems very simple but it doesn't work for me. maybe I'm missing something. (I'm able to configure open loop)

Thanks,
Michael David.

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Hello,
 The DFLL needs a ~32KHz reference clock however the output frequency must be 48MHz.

 

So, to configure DFLL48M you need to input it with 32.768Khz internal oscillator.

See picture below 

 


I hope this works to you.
Good luck..

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beingmachine wrote:
the output frequency must be 48MHz.

I missed that at first when I started with the D20/D21/R21 !

 

blush

 

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 Your answer helped me generate close loop 48M with 32K low power clock, and with external 32K clocks. smiley

I tried to use it with the High Accuracy internal 32K with no success. Do I need to calibrate the high accuracy clock?

here is my configuration of the accurate 32K am I missing something?Accurate Clock Configuration

 

Thanks,
Michael David.

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I don't know the SAM and have no idea of what you are doing.  That never stopped me from offering free advice though.  smiley

 

I see you have "Enable 32kHz Output" checked.  What do you get if you don't check that?

 

On the Xmega, the RTC often uses 32kHz divided by 32 giving 1024 Hertz.  1024 Hertz is what the Xmega DFLL uses.

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Hello @Michgo8 Glad it works! 
 

I tried to use it with the High Accuracy internal 32K with no success

I really don't know why it's not working for you with that clock, I don't have my ATSAMD21-Xplained-Pro kit along with me right now. I can't test.. (May be you should create a new thread)

 

By the way, can you post screenshots of your configuration with Clock settings ,GCLK and CPU from which you successfully generated close loop 48M with 32K low power clock, and with external 32K clocks please.

 

Hello @Steve

 

I see you have "Enable 32kHz Output" checked.  What do you get if you don't check that?

Simple,  oscillator will not provide output from that crystal..

 

On the Xmega, the RTC often uses 32kHz divided by 32 giving 1024 Hertz.  1024 Hertz is what the Xmega DFLL uses.

I have learnt from Microchip Engineer, that DFLL of ATSAMD21 needs to be sourced with 32.768Khz.

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Hi, I attached the configuration files :

test14 - external 32K (works)

test13 - internal 32K (don't work.

,regards

 

Attachment(s): 

Thanks,
Michael David.

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Hello David,
I am sorry for late responding, if you still have problem with DFLL, then use the configuration of DFLL (see screenshot attached) i am using in Close loop. I have tried with all 32.768Khz Oscillators and it's working great.
Hope it helps

 

Attachment(s):