I am using the xmega 128A3U in an application that supports a graphics display that is controlled with a SPI interface. I also am using a Cypress flash memory device to store the graphics images. This flash memory is also controlled with SPI. The graphics display and flash memory are located on separate SPI ports.
The system initializes the system clock to 8 Mhz at boot and the application runs at this speed for 99% of the time. At some point when the display needs an image read from flash and written to the screen, I reinitialize the PLL to bump up the speed to 32 MHz (SPI = 16 MHz) read the flash and write to the screen to provide a fluid screen update. Once the screen update is complete, I go back to 8 MHz. The reason for the dual clock speed approach is due to EMI performance, which I will not go into further.
The approach works well. I make sure that I check the PLL to ensure that the clock is ready before the data exhange.
My question is, after the clock has been changed between frequencies does anyone know of any 're-initializing' of the SPI port that would be necessary. Are there an caveats that I should be cautious of when attempting this clock changing. I've seen a couple of flaky issues that I cannot explain and am wondering if I am missing something subtle.
I would appreciate you opinions of potential subtle problems with this approach.