I was wondering if anyone has seen or heard of any recent production issues regarding this flavor of Xmega controller. I have been working on a product that has been in production over the last year and all of a sudden we are having an issue that I cannot find a solution for and am suspecting faulty parts.
We have witnessed a small handful of boards using the 128A3U Xmega processor incorrectly reading the data back on the MISO line (Port D ) connected between the Xmega and an S25FL512S flash memory part. I have probed the pins directly at the Xmega port D where the SPI lines are being routed. An external logic analyzer/protocol analyzer has verified that no electrical timing specifications are being violated and the proper data is being presented to the Xmega MISO line but the data is being interpreted incorrectly. We are seeing about A 1% failure as of recent. We have been using the same firmware and hardware design for about a year and have not seen this problem before.
The MOSI line is correctly exercising the Flash Memory part and with instrumentation, the data from the flash memory is properly present directly at the MISO pin of the Xmega. However, when the data is read from the SPI Data registers it does not match the known data which was correctly recorded with the logic analyzer..
The only sample that I have tested has a date code of 1651.
Below is a copy of the signature row information for this 1651. I have no idea how to interpret this data but if anyone has heard of similar issues I would appreciate hearing from you.