I realize that clearing the global interrupt bit in SREG disables all interrupts. But does it mean interrupt requests indicated by flags will get wiped out or that they will merely be postponed until the global interrupt bit is set? The context is as follows. I need two interrupts on ATtiny85. One interrupt is on timer0 compare match, and the other one handles rising edges on INT0.
... TIMSK = 1<<OCIE0A; // interrupt on compare match MCUCR |= 1<<ISC01 | 1<<ISC00; // rising edge interrupt on PB2 GIMSK |= 1<<INT0; // rising edge interrupt on PB2 ... ISR(TIMER0_COMPA_vect) { // compare match interrupt ... } ISR(INT0_vect) { // PB2 rising edge ... }
I am concerned about the situation when both interrupt requests overlap. Let's say it happens and execution jumps to ISR(INT0_vect). When compare match occurs, the flag bit OCF0A will be set in TIFR, but the global interrupt will be disabled inside the interrupt routine, so nothing will happen. However, when ISR(INT0_vect) is finished and the global interrupt bit is set in SREG, will the micro continue to ISR(TIMER0_COMPA_vect)? Or will it clear OCF0A and simply skip the interrupt for good? The datasheet says the following:
...if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.
It seems that the compare match interrupt should happen when ISR(INT0_vect) is finished. But I've misread the manual in the past, so I'm not 100% confident I'm reading it right. It would be fantastic if some one could confirm my interpretation.