I'm trying to implement I2C master using the XDMAC controller of the SAME70.
My TWI DMA software implementation is based on the E70 manual chapter 220.127.116.11 Using the DMA Controller (DMAC) in Master Mode.
So far I succeeded in implementing TWI master read/write with polling and master write using XDMAC but failed on master read using XDMAC.
On the scope I can see that the first byte transferred on I2C seems to be fine but the second byte read is stuck after the 7th clock cycle. Looks like the DMA hardware hung up and the question is how this can happen.
The master ties the clock low forever until if I restart the master. Then the clock goes high again. No XDMAC interrupt is generated if the read hangs up although all XDMAC interrupt bits including bus errors are activated.
The following screen shots show the first byte receive timing and the second shows the incomplete second byte. Any ideas ?