Why no Double Buffer Xmt in SPI engine?

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I realize that if you need to a double buffered transmitter in SPI you have to use one of the USARTs in master SPI mode but I cannot understand why the standard SPI port does not have a configuration mode to support buffered xmt.  Has this ever been explained or does any one understand why?  It seems there are some spare bits that could be used for setting this mode, yet allow for backwards compatibility.  If anyone has any knowledge, I would appreciate it.

Thanks

Jim

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rfdes wrote:
there are some spare bits that could be used for setting this mode

The bits to select it are probably not the Big Thing - it would be the logic to implement it ...

 

 

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The AT89LP4052 has it. So does the AT89S8253. The earlier AT89S52 does not have it.
The legacy Tiny, Mega, Xmega do not have it.
The legacy PIC16, PIC18 do not have it.
I think that the new Tiny817 does have it.
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Yes, USART_MSPI works very well. How often do you ever want to implement a Slave on a Mega?
USI on a Tiny works fine as a Slave. ATtiny2313A, 1634, 4313, ... have got USART_MSPI.
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I am quite happy to have a dedicated SPI Master or a dedicated SPI Slave.
I can never understand the attraction of haywire-ability. It must be the most common reason for SPI tears at bedtime.
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David.

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I didn't mean to imply that setting a bit was all that was needed.  The extra logic would be fairly straight forward and Atmel has already done this in the past with other parts. 

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Just as you use interrupts and ring buffers to add extra buffering to UARTs is there some reason you cannot do the same to add buffering to any peripheral. The AVRs are small, simple micros. The peripherals are kind of "RISC" like the CPU is! If you want complex peripherals you need to program around them (or trade up to things like Xmega that add stuff like DMA etc). At the end of the day one of the main attractions is (was?) the cheap cost of the silicon - that is maintained by keeping the die area smaller.

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You can try every trick in the book. The SPI peripheral always has gaps.
A buffered SPI could produce gap-less transmission just like the USART.
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Surely die size is dependent on number of bonding pads and the size of the output driver silicon.
The silicon required for peripheral logic is small compared to Flash and SRAM real estate.
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You only have to look at the ARM Cortex chips. Complexity and price in comparison to AVR.
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Regarding innovation, the Xmega appeared in 2007. The same year as Cortex-M3.
Until the Tiny817, nothing new in Tiny/Mega AVR since about 2004.
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I suspect that the poor SPI is down to the difficulty in implementing Slave response and performance especially with receiving a gap-less sequence.
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David.

Last Edited: Thu. Aug 17, 2017 - 12:40 PM