Hi Everybody!
Anybody has experience to handling overflow in case of TC input capture?
The problem is CC has 3 stage event storage, the counter itself, the CCbuf and the CC.
A program can read only the CC event.
But the overflow IT is bond to counter.
So the overflow "event" belong to CC is delayed with 0 to 2 CC event!
Anybody has exeprience how it possible to handle it?
Thanks for any advise.
Which device you are talking about ?
I think this is common issue for all Xmega. Because all have TC and have input capture feature. If it is interesting then I use Xmega A3.
Some clarification
I mean overflow of counter value during input capture.
Unfortunately the documentation use word “overflow” for CC and CCbuf overflow (unreaded, and new event lost) and for counter overflow too.
Can you clarify what you are trying to achieve? I believe that all of the input capture channels on the xmegas are routed through the event system and when an event is serviced (guaranteed to be within 2 peripheral clock cycles) the timer count is copied into the CCxBUF register and if the buffer is valid and that CC channel is enabled the CCx interrupt flag is set. If the counter overflows it should reset to zero and if that is the count value when the event is processed you will store zero in your CCx register. Are you trying to do something in the overflow interrupt??? Remember that the input capture is run off the event system and it will be many cycles before you can enter an overflow interrupt.
What do you mean by this?
So the overflow "event" belong to CC is delayed with 0 to 2 CC event!
I have pulses to identify.
This pulses are constructed by n binary 0 and n binary 1.
The minimum pulse time is 1+1=2mS (I hope).
But n is 1 to 1000.
I need accuracy best than 0,5%.
This mean I cannot count it using 16 bit (15 bit) timer. I need 30 bit for.
As solution I try to use 16 bit (15 bit) TC + overflow interrupt solution.
If one (or more) overflow occurred during capture of input event, then I must add count to CC value.
