UC3 I2S output starts with random LRCK

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Hi guys, 

 

I use the SSC for I2S TX on the AT32UC3A3256. This has worked very well for a long time, and I have products in the market with it. But recently I've seen random swaps in left and right output from the I2S output. This translates to LRCK (= TX_FRAME) having seemingly random polarity inversion. 

 

So my question is: How do I start up the I2S transmitter from a known LRCK state? As you may know, LRCK becomes 0 one BCLK tick before the start of left-channel data, and LRCK becomes 1 one BCLK tick before the start of right-channel data. In my case there seems to be random LRCK inversion. 

 

My code does chooses from two external crystal oscillators, and the XO/BCLK division may change depending on source and sample rate. But the system has a fixed relationship between BCLK and LRCK for the I2S output. 

 

Even though the BCLK frequency may change, this line used to be called only once:

ssc_i2s_init(ssc, 48000, 32, 32, SSC_I2S_MODE_STEREO_OUT_STEREO_IN, FPBA_HZ);

 

But if I call it again manually, pure chance seems to decide if I get proper L/R split or LRCK inversion. I'm able to trig my digital 'scope when that function is called, and then look at LRCK. There is no obvious link between the value of LRCK at before calling ssc_i2s_init() and whether or not I get L/R inversion afterwards. 

 

The second parameter is disregarded in ssc_i2s_init. The function is originally from the software framework. When I look at it, I don't find any reference to starting LRCK / TX_FRAME at a known state. 

 

 

Thanks,

Børge

 

 

 

 

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I was able to trace things a bit further, and I believe it is the onset of pdca_enable(PDCA_CHANNEL_SSC_TX); and friends which must be timed to the polarity of LRCK. 

 

I assume from this that the ssc pulls one word from the pdca for every left and every right sample, instead of pulling two words from it for every left sample. (Which would be the more I2S-centric and also slightly more complex thing to do.) 

 

 

Børge