I've got a GPS clock based on the MAX6951 and an ATTiny841. The hardware uses PA7 as an ICP pin, which is unfortunate, because it's also !SS for the SPI port. 17.3.2 says that if !SS becomes low, then SPI master mode is aborted and the MSTR bit is cleared. Most of the time (but not all the time), A7 is low.
What I'm seeing instead is that the SPI system seems to get wedged, necessitating writing 0 to SPCR and then _BV(SPE)|_BV(MSTR) again.
As a workaround, I'm reading PINA7, writing that value to PORTA7 and then turning A7 into an output pin (this avoids the output clashing with the current state of the line, which is an output from another chip), then writing the correct bits to SPCR. When the transaction is done, I write 0 to SPCR and clear DDA7. This works. But if I attempt instead to set SPCR up at initialization time, I must write 0 to SPCR followed by the correct value after turning A7 into an output. Merely forcing MSTR on isn't enough. Neither is writing the correct bits to SPCR. You must write a 0 to SPCR and then reset it.
Are there any known errata with the SPI functionality of this chip with regards to !SS in Master mode?