Logic Level INT0 excessive triggering - What voltage is LOW

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I am encountering a logic level issue with INT0 on a Tiny44. I am using the external interrupt to detect the beginning of an analog wave form then triggering a sample/hold circuit 20mS later.

See attached Word Doc for scope pictures...

What I am find is that for input voltages above 1.8V the INT0 behaves as I would expect triggering the interrupt while low starting the timer0 and generating a trigger pulse in the proper position.

However below 1.8 to 1.7V the int0 triggers excessively. I thought that the logic level for a low was 0.8V or less....

I am feeding the analog signal through a 180Ohm series resistor: The wave form is identical on both sides of the resistor so I don't think that I am loading the signal down with the pin.

DDRB = 0x00; // all inputs
PORTB = 0x0F; // all pullup enabled

My INT0 interrupt routine starts timer1 and presets the TCNT0 to a preset value. As long as INT0 is low the TCNT0 is reset. When the signal leaves ground INT0 is supposed to stop triggering its interrupt and allow the TIMER0 to generate output pulses using COMPA/B and the OVF interrupts. This would let me detect the rising edge of the signal.

Works well as long as I have a large enough signal.

It just seems as if the Logic Level for a LOW is 1.8V or less....

A simple work arround would be to just start TIMER0 on the falling edge and disable INT0 interrupt until the TIMER0 completes its waveform. But I am close to making this work.

I would like to hear some suggestions and comments.

Thanks

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For most CMOS devices, the logic trip level is half VCC. The old 0.7 v values was for TTL levels. The datasheet should have a spec for this value. Remember - this value has a tolerance. If you want better accuracy, use the analog comparator (if your device has it).

Why are you using logic level trigger Should you not use edge trigger?

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TIRH wrote:
...

However below 1.8 to 1.7V the int0 triggers excessively. I thought that the logic level for a low was 0.8V or less....

I am feeding the analog signal through a 180Ohm series resistor: The wave form is identical on both sides of the resistor so I don't think that I am loading the signal down with the pin.

You are misinterpreting the data sheet.

INTO expects a digital signal at its input - in order to guarantee that it will be interpreted correctly as a low you have to ensure it is below 0.2VCC. However the actual threshold may be as high as 0.8VCC.

Typically the threshold for CMOS devices is about 50% of the supply voltage. If you have an analog signal you need to send it through a comparator first to determine the threshold voltage. Some devices have such a comparator internally, I couldn't find a data sheet for an ATTiny44 (is that the correct number?) to see whether it had one.

kevin

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There is a small amount of hysteresis on port pin inputs, but apparently not enough to make your design work. The problem is that regardless of where the actual threshold voltage is, it is a single voltage. If your signal has noise on it, it will not cleanly pass through that threshold voltage, but will bounce up and down around it as it trends by.

You can add hysteresis by using an output port pin to create positive feedback. Place a resistor from the output pin to your input pin (and leave your other input resistor in place. The ratio of the two resistors controls the amount of hysteresis you get. When you get your falling edge interrupt, set the output pin low, when you get a rising edge interrupt, set the output pin high.

You could also use a capacitor for the positive feedback and set the RC time constant to a suitable value. This provides hysteresis without affecting the threshold voltage.

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Hi,

With digital CMOS input the region between true LOW and true HIGH is not allowed.
For sure when a signal changes stat it will travel through this region but there is also a min. rise and falltime spec´d.

If you stay too long in this not allowed region you may find some inputs to oscillate. (I don´t know if this can happen with AVRs)

Klaus
********************************
Look at: www.megausb.de (German)
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Kartman wrote:

Quote:
Why are you using logic level trigger Should you not use edge trigger?

The ATtiny44 is configured to use its internal RC clock. INT0 is configured for low detection as this does not require an external clock reference for edge detection.

A little more background on my project:
I will be multiplexing through upto 16 channels of analog signals each pulsing at 1 second intervals. The microcontroller will detect the data pulse and trigger a sample and hold of the midlevel voltage portion of the signal. Finally a trigger pulse will be generated to activate an external data logger which will record the sampled voltage and the mux address lines.

I am currently using all I/O pins for addressing & enabling a mux, 2 data sample/hold (one inversed), a DATA (INT0) line, a DAQ external trigger and 3 binary inputs.

kevin_white wrote:

Quote:
Typically the threshold for CMOS devices is about 50% of the supply voltage. If you have an analog signal you need to send it through a comparator first to determine the threshold voltage. Some devices have such a comparator internally, I couldn't find a data sheet for an ATTiny44 (is that the correct number?) to see whether it had one.

You are correct the ATtiny24/44/84 has an ADC / Comparator built in. as previously mentioned I am using all pins. But I like the idea of using a comparator to adjust logic levels. I am going to look into placing one on the DATA input line.

ScottKroeger wrote:

Quote:
You can add hysteresis by using an output port pin to create positive feedback

I like the idea. I would have to also add a diode to prevent backfeeding voltage onto the data line which is feeding the LF398 Sample/Hold input. My Sample/Hold output is available as a feedback source. I would just have it turn on and sample (Track) the data line earlier and for a longer period (30ms vs 10ms). This would mean that the sample and hold would have to track a wider voltage swing across a larger portion of the signal. But since the signal stabilizes quickly the LF398 should be tracking pretty close if not dead on by the end of the sample pulse.

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You are going to add components to adjust a logic level? Suit yourself; it is putting the cart before the horse IMO.

When using level triggering, the typical approach is to disable the interrupt and clear the pending when fired. This really isn't any different in concept than UDRE and EERIE/EEWE.

Lee

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Quote:
The ATtiny44 is configured to use its internal RC clock. INT0 is configured for low detection as this does not require an external clock reference for edge detection.

It's not an external clock you need, it's just that the CPU must be clocking. If you don't put the CPU to sleep there is no reason not to use edge interrupts. If you must sleep, that's reason to use level triggering.

After looking at your waveforms, I wonder what the maximum repetition rate is for this pattern. Can you just catch the initial falling edge, then disable interrupts and set a timer for 20ms, sample the signal, send the trigger, then wait another 20ms or so before re-arming? Without knowing the voltage range for the analog signal after the initial trigger, it's hard to say whether you can use a logic input, whether hysteresis can solve your problem, or whether another method is needed.

From what I see, time appears to be the best filtering mechanism you have.

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TIRH wrote:
However below 1.8 to 1.7V the int0 triggers excessively. I thought that the logic level for a low was 0.8V or less....

figure from datasheet:
http://avr123.nm.ru/img/02_20log...

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I'm going to take another look at rising edge detection on INT0 with the system clock but it still may not work if the analog signal isn't high enough to generate a HI logic level.

As I have 100% pin usage it is most likely I will have to add hardware. (Either to impliment logic level conversion or to free up a pin for software controlled feedback)

Hardware level conversion might be the silver bullet. It also has the benefit of allowing the usage of trim pots to adjust trigger and hysteresis levels.

Thanks All for the ideas