E5 SPI buffer modes

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mojo-chan
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Posted by mojo-chan: Thu. Oct 20, 2016 - 08:02 AM
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I'm trying to understand the XMEGA E5 SPI peripheral's buffer modes. The manual states:

 

 Buffered mode 2:

The SPI module is single buffered in the transmit direction and double buffered in the receive direction. A byte writ-
ten to the transmit register will be copied to the shift register when the SPI is enabled. Then, one SPI transfer must
be completed before the data is copied to the shift register.

 

That's not very clear to me. In mode 1 there is a dummy byte shifted out, and in mode 2 there isn't. But what does the third sentence mean, about one transfer being completed before data is copied to the shift register?

 

My guess is that it refers to reading bytes, as in you must wait for the first byte written to clear the FIFO before a byte is available to read.

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AVR Microcontrollers, AVR and XMEGA
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mojo-chan
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Posted by mojo-chan: Sun. Feb 12, 2017 - 06:38 PM
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Mega bump but I think I get it now.

 

 Buffered mode 1:
The SPI module is single buffered in the transmit direction and double buffered in the receive direction. A byte writ-
ten to the transmit register will be copied to the shift register when a full character has been received. When
receiving data, a received character must be read from the DATA register before the third character has been
completely shifted in to avoid loosing data.
 Buffered mode 2:
The SPI module is single buffered in the transmit direction and double buffered in the receive direction. A byte writ-
ten to the transmit register will be copied to the shift register when the SPI is enabled. Then, one SPI transfer must
be completed before the data is copied to the shift register.

Buffer mode 1 waits for one byte to be received before loading the transmit shift register. Buffer mode 2 loads the shift register immediately.

 

Mode 1 seems good for slave operation, when you want to be synchronized with the master. Mode 2 seems to be aimed at master mode or non-standard SPI modes.

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