SPI bus, daisy chained slaves, time calculation?

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hi,

 

can some check if I'm calculating the time between the Master and last Slave correctly?

 

e.g.

- SPI is set to run at 4MHz

- There are 8 daisy chained slave devices, i.e. Master MOSI - (MOSI slave1 MISO) - (MOSI slave 2 MISO) - and so on til slave 8

- There is only one CS line which enables/disables all slaves simultaneously.

 

How long will it take for one byte from Master to be received by slave 8.

 

My calculation:

 

1bit = 1/4MHZ = 0.25uS

1byte = 8 x 0.25 = 2uS

 

So 2uS to get a byte to slave 1,

and to slave 8 = 2 x 8 = 16uS?

 

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There's an extra clock or two between bytes with the spi peripheral. You also need to consider how fast your code will respond to a new byte. 2us isn't much time - 32 clocks. This can get chewed up in the interrupt response.

Last Edited: Thu. Dec 15, 2016 - 01:52 AM
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Normally SPI slaves are connected in parallel and selected with separate /SS pins.....  rather then daisy chained!

 

https://upload.wikimedia.org/wik...

 

 

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ki0bk wrote:
Normally SPI slaves are connected in parallel and selected with separate /SS pins..... rather then daisy chained!

Indeed, that is my approach/experience.

 

Some will daisy-chain e.g. shift registers and then use the AVR's SPI peripheral to drive them.  OP was very vague as to what these SPI slaves are...

 

-- if AVRs then the AVR slave will need to complete the slave reception, switch to master, pass on the packet, then resume slave mode.  So the AVR master would need to wait between bytes for the slave to be again ready.  IMO not a practical setup.  (I indeed have an app with a similar setup but I use the USART which is full duplex.  So e.g. the first slave can continue listening and processing more incoming message bytes wile retransmitting downstream.)

 

-- If shift registers, then daisy-chain should work OK.  Up to you whether a single e.g. '595 LATCH if outputs or multiple.  If e.g. '165 inputs, that is left as an exercise for the student.

 

Kartman wrote:
There's an extra clock or two between bytes with the spi peripheral.

 

-- If USART-as-SPI-master then you are at least multiple-buffered for transmit, right?

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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-- If shift registers, then daisy-chain should work OK. Up to you whether a single e.g. '595 LATCH if outputs or multiple.

 

Yes, I have done that before with shift registers, but for my future project I will be using MCU's, atmega8, so you other comment is very relevant:

 

-- if AVRs then the AVR slave will need to complete the slave reception, switch to master, pass on the packet, then resume slave mode. So the AVR master would need to wait between bytes for the slave to be again ready. IMO not a practical setup.

hmm, then I could use a octal tri-state buffer for the MISO lines of the slaves to isolate them from the MISO line, this way I could enable all of the slaves together so that they will receive the byte on the MOSI line simultaneously. Could it be a problem for the Masters MOSI output to drive 8 slave MOSI inputs?

 

 

 

 

 

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electronaut wrote:
hmm, then I could use a octal tri-state buffer for the MISO lines of the slaves to isolate them from the MISO line, this way I could enable all of the slaves together so that they will receive the byte on the MOSI line simultaneously. Could it be a problem for the Masters MOSI output to drive 8 slave MOSI inputs?

???  You'll have to give me a circuit diagram of this proposed layout.

 

IMO/IME you are making it much too hard on yourself.

 

First, the choice of Mega8 for slaves.  AVR8 slave SPI is really conducive to very simple protocols.

 

And that model has many fewer features than the newer generation '88 family.

 

And the newer 'PB family has dual USARTs, for example, where you can use USART to pass the message down the stream.

 

Use of SPI implies short distances between nodes.  Why not just use one micro?

 

That said, I have many apps with "modules".  But I have the master poll the slaves in turn with USART.  And you can construct "broadcast" messages that all slaves will see at the same time.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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??? You'll have to give me a circuit diagram of this proposed layout.

I don't have on yet, but the following picture is pretty much how it's going to be, except more slaves and a 3 to 8 decoder for the CS lines:

 

http://hades.mech.northwestern.edu/images/6/6a/Spi-diagram.png

 

 

First, the choice of Mega8 for slaves.  AVR8 slave SPI is really conducive to very simple protocols.

Well I have a few laying around so for now I will use them, or at least for prototyping.

And that model has many fewer features than the newer generation '88 family.

I don't think I need many features for my project, just UART and SPI, 8KB of flash should be enough.

 

And the newer 'PB family has dual USARTs, for example, where you can use USART to pass the message down the stream.

 

I've looked at the at the 88PB, it has only one UART but two SPI modules.

http://www.atmel.com/devices/ATM...

 

In any case in my project the UARTs of the m8's are used for outside communication, MIDI, at 31250 baud rate.

 

Use of SPI implies short distances between nodes.  Why not just use one micro?

 

Yep, all the nodes be in one device, i.e. small distance from each other.

 

I need 8 UARTs, plus I think that it will be faster for individual MCU's to do the UART (MIDI) filtering, etc.. and just use a master MCU that will set the filtering parameters and send them (by SPI) to the slave m8's that will do the actual UART receive/process/filter/send data tasks.

 

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I've just use the product search on the Amtel website and found ATxmega64A1, it has 8 UARTs, but it's a XMEGA and I've only dealt with atmegas and attinys. I'll have to look more into it, perhaps I could use it for my project.

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That is NOT daisy chain. That is the way that SPI is usually configured. All MISO connected together, all MOSI connected together, all SCLK connected together, separate chip selects.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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electronaut wrote:
- There are 8 daisy chained slave devices, i.e. Master MOSI - (MOSI slave1 MISO) - (MOSI slave 2 MISO) - and so on til slave 8 - There is only one CS line which enables/disables all slaves simultaneously.

We learned that in the first post.  Then I asked

theusch wrote:
You'll have to give me a circuit diagram of this proposed layout.

...and the response bears no resemblance to the original description:

 

http://hades.mech.northwestern.edu/images/6/6a/Spi-diagram.png

 

I'm out.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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theusch, the original layout in mind that I had was daisy chained:

 

http://dlnware.com/sites/dlnware.com/files/images/spi_daisy_chain.png

 

but then you commented:

 

-- if AVRs then the AVR slave will need to complete the slave reception, switch to master, pass on the packet, then resume slave mode. So the AVR master would need to wait between bytes for the slave to be again ready. IMO not a practical setup.

so I responded:

 

hmm, then I could use a octal tri-state buffer for the MISO lines of the slaves to isolate them from the MISO line, this way I could enable all of the slaves together so that they will receive the byte on the MOSI line simultaneously. Could it be a problem for the Masters MOSI output to drive 8 slave MOSI inputs?

And I posted the image above of a standard SPI bus setup (not daisy chained). So if tri-state buffers are used on the MISO lines of the slaves (to disconnect them from the MISO line), I can enable them all at once and the master could send a byte to all of them in one transaction, except that I don't know if the masters MOSI output can drive 8 slave MOSI inputs at once. From what I understand it should be ok since when the pins are configured as inputs the impedance is very high, but maybe there are some factors that should be considered?

 

 

 

 

 

 

 

 

 

Last Edited: Fri. Dec 16, 2016 - 03:41 PM
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The buffer should not be needed, the master should be able to drive multiple (8 or more) inputs at the same time.

Your 3-to-8 decoder on the /CS lines may have a problem, as you need a way to NOT select any of the slaves.  Perhaps only have 7 slaves with one position not used, or .....

 

Anyway, that sounds like it can be done.  Let us know how the project goes, and come back if you have any other issues.

 

Jim

 

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Your 3-to-8 decoder on the /CS lines may have a problem, as you need a way to NOT select any of the slaves. Perhaps only have 7 slaves with one position not used, or .....

 

Yep, I thought about it. So I think I will tie all CS pins together so that the slaves will receive the byte from the master at the same time. The byte itself will contain the address of the slave that needs to process it, e.g. 3 bits for the address and 5 bits for a specific command.

 

And for slave to master communication I will use the 3-to-8 decoder for enabling/disabling the 8 separate tri-state buffers connected to the MISO lines of the slaves.

One thing I don't know yet is if there are octal tri-state driver IC's available that let you enable/disable single channels at a time, or better yet a tri-state driver with 3-to-8 interface in one package.

 

p.s. hmm, did not think about, but for the MISO line I think I can just use a multiplexer, e.g. CD4512

Last Edited: Fri. Dec 16, 2016 - 06:14 PM
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I still say you are making things too hard.

 

Start with the overall approach:  your way is a number of small microcontrollers close by.  Compare to single larger microcontroller.  Less cost, board space, power, ...

 

I mentioned that I'd tend to use USART and RS485 and multi-drop slaves.  Often with MPCM.

 

On to the "too hard" part -- why would you want a decoder and multiplexer and so forth when the slaves control the direction of their MISO?

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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I still say you are making things too hard.

You're right.

 

I got carried away from the original idea that communication would only go one way, master to all slaves at the same time, in which case I don't need any multiplexers  or 3-to-8 decoders since the MISO pins on the slaves will be left unconnected from the SPI bus.

 

Start with the overall approach: your way is a number of small microcontrollers close by. Compare to single larger microcontroller. Less cost, board space, power, ...

For now I only know how to prgram AVR megas, not Xmegas, and there is no mega MCU with 8 UARTs.

Another thing is the type of package, I prefer DIPs or SMD's with the least amount of pins since I solder by hand.

 

On to the "too hard" part -- why would you want a decoder and multiplexer and so forth when the slaves control the direction of their MISO?

Assuming that I will also need slave to master communication, then a 3-to-8 decoder will just reduce the number of pins on the master mcu needed to separately select each of the 8 slaves.

 

 

 

 

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electronaut wrote:

Assuming that I will also need slave to master communication, then a 3-to-8 decoder will just reduce the number of pins on the master mcu needed to separately select each of the 8 slaves.

 

You can get two way data flows, using your daisy-chain as a ring.

When SS is high, all slaves load their outgoing data to SPI, and then Master pulls SS low, and all that data shifts into the master, as the master sends info to slaves.

Each SPI slave acts like a 8-bit shift register, and with 8 slaves, 64 clocks are needed to ripple the data to load all of them.

SS then goes high, and every slave reads their SPI Rx register.

Every frame manages 64 bits out and 64b back, but the reply is delayed and is from the previous frame.