A bit of fun - new way to program AVRs - beta testers invited!

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MannImMond wrote:

DEVXML-909

Wrote this just to check for "long" captions which might indicate faults:

import os
import xml.etree.ElementTree as et

lenchk = 80

for f in os.listdir("."):
    if ".atdf" in f:
        print("File: ", f)
        tree = et.parse(f)
        root = tree.getroot()
        modules = root.find("modules")
        for mod in modules.findall("module"):
            rg = mod.find("register-group")
            for reg in rg.findall('register'):
                try:
                    captn = reg.attrib['caption']
                except KeyError:
                    captn = "none"
                if len(captn) > lenchk:
                    print(reg.attrib['name'], captn)
                for bf in reg.findall('bitfield'):
                    try:
                        captn = bf.attrib['caption']
                    except KeyError:
                        captn = "none"
                    if len(captn) > lenchk:
                        print(bf.attrib['name'], captn)

When I run that I get:

File:  AT90CAN128.atdf
File:  AT90CAN32.atdf
File:  AT90CAN64.atdf
EEAR EEPROM Read/Write Access Bytes - Only bit 10..8 are used in AT90CAN64 - Only bit 9..8 are used in AT90CAN32
File:  AT90PWM1.atdf
File:  AT90PWM161.atdf
File:  AT90PWM216.atdf
File:  AT90PWM2B.atdf
File:  AT90PWM316.atdf
File:  AT90PWM3B.atdf
File:  AT90PWM81.atdf
File:  AT90USB1286.atdf
File:  AT90USB1287.atdf
File:  AT90USB162.atdf
File:  AT90USB646.atdf
File:  AT90USB647.atdf
File:  AT90USB82.atdf
File:  ATmega128.atdf
File:  ATmega1280.atdf
File:  ATmega1281.atdf
File:  ATmega1284.atdf
File:  ATmega1284P.atdf
File:  ATmega1284RFR2.atdf
File:  ATmega128A.atdf
File:  ATmega128RFA1.atdf
File:  ATmega128RFR2.atdf
File:  ATmega16.atdf
ADATE When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
File:  ATmega162.atdf
File:  ATmega164A.atdf
File:  ATmega164P.atdf
File:  ATmega164PA.atdf
File:  ATmega165A.atdf
File:  ATmega165P.atdf
File:  ATmega165PA.atdf
File:  ATmega168.atdf
File:  ATmega168A.atdf
File:  ATmega168P.atdf
File:  ATmega168PA.atdf
File:  ATmega168PB.atdf
File:  ATmega169A.atdf
File:  ATmega169P.atdf
File:  ATmega169PA.atdf
File:  ATmega16A.atdf
ADATE When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
File:  ATmega16HVA.atdf
BGD Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled.
PA1DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
PA0DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
CADEN When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
CADSI The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
CADSE When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
File:  ATmega16HVB.atdf
CADEN When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
CADSI The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
CADSE When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
PA1DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
PA0DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
File:  ATmega16HVBrevB.atdf
CADEN When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
CADSI The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
CADSE When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
PA1DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
PA0DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
File:  ATmega16M1.atdf
File:  ATmega16U2.atdf
File:  ATmega16U4.atdf
File:  ATmega2560.atdf
File:  ATmega2561.atdf
File:  ATmega2564RFR2.atdf
File:  ATmega256RFR2.atdf
File:  ATmega32.atdf
ADATE When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
File:  ATmega324A.atdf
File:  ATmega324P.atdf
File:  ATmega324PA.atdf
File:  ATmega324PB.atdf
File:  ATmega325.atdf
File:  ATmega3250.atdf
File:  ATmega3250A.atdf
File:  ATmega3250P.atdf
File:  ATmega3250PA.atdf
File:  ATmega325A.atdf
File:  ATmega325P.atdf
File:  ATmega325PA.atdf
File:  ATmega328.atdf
File:  ATmega328P.atdf
File:  ATmega328PB.atdf
File:  ATmega329.atdf
File:  ATmega3290.atdf
File:  ATmega3290A.atdf
File:  ATmega3290P.atdf
File:  ATmega3290PA.atdf
File:  ATmega329A.atdf
File:  ATmega329P.atdf
File:  ATmega329PA.atdf
File:  ATmega32A.atdf
ADATE When this bit is written to one, the Timer/Counter2 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset.
File:  ATmega32C1.atdf
File:  ATmega32HVB.atdf
CADEN When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
CADSI The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
CADSE When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
PA1DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
PA0DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
File:  ATmega32HVBrevB.atdf
CADEN When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
CADSI The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
CADSE When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
PA1DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
PA0DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
File:  ATmega32M1.atdf
File:  ATmega32U2.atdf
File:  ATmega32U4.atdf
File:  ATmega406.atdf
CADEN When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
CADSI The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
CADSE When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
BGD Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled.
File:  ATmega48.atdf
File:  ATmega48A.atdf
File:  ATmega48P.atdf
File:  ATmega48PA.atdf
File:  ATmega48PB.atdf
File:  ATmega64.atdf
File:  ATmega640.atdf
File:  ATmega644.atdf
File:  ATmega644A.atdf
File:  ATmega644P.atdf
File:  ATmega644PA.atdf
File:  ATmega644RFR2.atdf
File:  ATmega645.atdf
File:  ATmega6450.atdf
File:  ATmega6450A.atdf
File:  ATmega6450P.atdf
File:  ATmega645A.atdf
File:  ATmega645P.atdf
File:  ATmega649.atdf
File:  ATmega6490.atdf
File:  ATmega6490A.atdf
File:  ATmega6490P.atdf
File:  ATmega649A.atdf
File:  ATmega649P.atdf
File:  ATmega64A.atdf
File:  ATmega64C1.atdf
File:  ATmega64HVE2.atdf
PA1DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
PA0DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
File:  ATmega64M1.atdf
File:  ATmega64RFR2.atdf
File:  ATmega8.atdf
File:  ATmega8515.atdf
File:  ATmega8535.atdf
ADATE When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
File:  ATmega88.atdf
File:  ATmega88A.atdf
File:  ATmega88P.atdf
File:  ATmega88PA.atdf
File:  ATmega88PB.atdf
File:  ATmega8A.atdf
File:  ATmega8HVA.atdf
BGD Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled.
PA1DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
PA0DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
CADEN When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
CADSI The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
CADSE When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
File:  ATmega8U2.atdf

 

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The ADATE bits were all fixed already the others look fine to me (albeit the long captions do look strange)

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MannImMond wrote:
(albeit the long captions do look strange)
Indeed ;-)

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Finally I seem to have my generator creating datasheet perfect bit patterns but I have one remaining question. Some of the XML has things like this:

        <register caption="Stack Pointer " name="SP" offset="0x5D" size="2" mask="0x07FF"/>

notice the mask="0x7FF" in that. It means "not quite 16 bits" (this is the mega168P in fact). So I cater for this when generating the individual bits:

	union {
		uint16_t reg; // (@ 0x5d) Stack Pointer 
		struct {
			unsigned int b0:1;
			unsigned int b1:1;
			unsigned int b2:1;
			unsigned int b3:1;
			unsigned int b4:1;
			unsigned int b5:1;
			unsigned int b6:1;
			unsigned int b7:1;
			unsigned int b8:1;
			unsigned int b9:1;
			unsigned int b10:1;
		} bit;
		struct {
			uint8_t low;
			uint8_t high;
		} halves;
	} _SP;

That is only creating bits b0 to b10 as it should, but the question is about the "halves": should "high" really be constrained as:

		struct {
			uint8_t low;
			unsigned int high:3;
		} halves;

so that it only effectively has 3 bits (8..10) accessible? Or just left as a complete byte? Opinions?

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I would leave it as 3 bits. Otherwise a write to .high would risk writing 'reserved' bits as 1, against datasheet recommendations.

 

Similarly, the .reg member should be 11 bits?

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

Last Edited: Fri. Apr 8, 2016 - 06:36 PM
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joeymorin wrote:
Similarly, the .reg member should be 11 bits?

Oh well spotted Sir. Completely missed that.

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I'd leave it as two bytes.  I've never seen code that reads the SP as anything other than 16bits, and I don't want to see bitmasking code if I try.

 

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I'd leave it as two bytes.  I've never seen code that reads the SP as anything other than 16bits, and I don't want to see bitmasking code if I try.

SPH/SPL do seem to be different from other I/O registers, now that I look at the datasheet:

 

 

The above is from the m16.

 

Although "the number of bits is implementation dependent", there is no explicit prohibition against writing unused bits.  As such, bit-fields seem unnecessary.

 

I am curious if there is any documentation anywhere which spells out what happens if SPH/L is set to a non-existent address.  I'm not referring now to addresses beyond the "implementation dependent" number of bits, but addresses which can in fact be expressed in the number of bits available.  Remember that SRAM on the m16 begins at 0x0060, so SPH/L need to be 11 bits.  The 1K SRAM ends at 0x045F, but SPH/L can address as high as 0x07FF.  Where will SPH/L point if it has a value of 0x460?  Will it point to the first byte of SRAM?  Will it point to r0?  Will it point some place else?  Or nowhere?  While a simple test program might reveal this, I do wonder if there is any documentation.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

Last Edited: Sat. Apr 9, 2016 - 02:03 PM
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Total votes: 1

I'm looking more at things like EEAR or PORT/PIN/DDR-C in the 48/88/168/328 for examples.

 

Wonder what happens if you write a 12 bit address to a 10 bit EEAR? The :10 protection would mask this happening.

 

Anyway I've already modified the code so I think I'll stick with it.

 

(who needs revision control anyway?!? ;-)

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