Unidentified low frequency components around 50Hz in a dc-ac inverter

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Hello,

 

Im designing microcontroller based dc to ac inverter based on unipolar PWM switching. The switching frequency used is 20khz and the sinusoidal frequency that I want to produce is 50hz with an amplitude of about 10V. I have an LC low pass filter at the output of my full bridge transistor circuit. The dc bus voltage is stiff and is around 40V. The sine wave reference given in the micontroller is based on a table lookup and contains only a sine wave of 50hz [made of 400 points].

 

When observing the output voltage im not able to get an exact 50hz signal. The signal produced contains additional 2 low frequency components at about 45 and 55 Hz however with smaller amplitudes (other than the 50Hz).

Im unable to trace the reason of why im getting such a signal, though the amplitude that im targeting (10V) can be observed. However this 10V is not directly seen due to the superposition of the 45 and 55hz components.

When removing the LC filter and observing the frequency spectrum of the voltage signal, more frequency components around the 50hz were observed. All the components were symmetrical to the 50hz and had smaller amplitudes as moving to the left or to the right of the 50hz component.

 

Has anyone experienced something similar before?

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Are you looking at the sidebands of a distortion in your sin table?

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I don't have any distortions in my sin table. When plotting it I'm getting a perfect 50Hz sin wave! Also looking at the frequency spectrum of the sin table shows a single component at the 50hz.

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Can you post schematic and code? 

 

David

 

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Sorry I can't post the code neither the schematics because I don't have the soft version of the schematic and the console that im working on is not connected to the internet.

 

Anyway, the hardware consists of a microcontroller connected to some driver ( with bootsrap functionality ) that drives the 4 transistors of the full bridge. As for the code, I have an infinite while loop running along with a timer that overflows/underflows every 50us. The unipolar PWM switching functionality is ran every 50us and is handled within the timer's function by updating 2 compare registers. Complementary outputs along with the deadtime feature are used.

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Like  Torby, those are suspiciously like modulation sidebands. How have you determined these frequencies? Spectrum analyzer? FFT?

 

Can you take a snapshot of the waveform? That would really help to understand what is happening. In particular, an oscilloscope "sweep" that is long enough to catch one or more cycles of a 5Hz amplitude variation. Trigger the scope to just catch the very highest peak of the waveform, then any amplitude variation (modulation) should be apparent.

 

Distortion would not produce frequencies like that. They  would all be harmonics of the fundamental. Instead, if those are modulation sidebands, then you have some sort of low frequency (5Hz) instability. Is there a feedback loop,  anywhere (where some process is modified depending on the output)? 

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Sat. Nov 21, 2015 - 05:38 PM
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Like  Torby, those are suspiciously like modulation sidebands. How have you determined these frequencies? Spectrum analyzer? FFT

 

I used the FFT feature on the oscilloscope to see them. In the figure I'm attaching you can see the time waveform in white and the FFT in purple (in the back).

 

Is there a feedback loop,  anywhere (where some process is modified depending on the output)? 

 

No, I'm not using any readings or inputs to determine the output values (the compare values of the timer)

 

Also note that when the LC filter is removed more sidebands near the 50Hz are observed having lower amplitudes and frequencies farther from 50 Hz.

 

Last Edited: Thu. Dec 10, 2015 - 02:59 PM
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Yes, it is being amplitude modulated, and that produces the "sidebands" you see.

 

The waveform, itself, looks distorted at first, but that is  due  to the low sample rate and can be ignored for now. I am suspicious of that negative  spike about 6.5 divisions from the trigger. 

 

First question: What does your filter look like and what is its corner frequency?

 

Second question: Look at the input  to your filter. Is the PWM signal constant amplitude? If it is, then you are looking at something that is  modulating the PWM process, itself.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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The peaks at 45/50/55 Hz sound like 'jitter' in the PWM, or simply phase noise due to a mismatched PWM frequency and sample rate.  What speed are you running the AVR?  What is the exact timer config?  Are you using an interrupt to update the compare registers from a lookup of the sine table?  Show some code.

 

As for the other components seen after removing the LC, those are the result of the PWM signal itself.

 

You say you're updating every 50 us, which get's us the 20 kHz you've mentioned.  At 400 samples, a 50 us sample time yields the 50 Hz fundamental you're after, so this makes sense.  But that's the >>sampling<< rate, not the PWM frequency.  What is the PWM frequency?  You haven't given enough information, but let's make some assumptions:

  • ATmega at 16 MHz cpu clock
  • TIMER1 running with no prescaler
  • 8-bit PWM

 

So the PWM clock will be  62.5 kHz.  Not 20 kHz.  If you're updating the compare match registers at a rate which is not a multiple of the PWM clock, you will see artefacts.  The nature of the artefacts you will see will depend upon the relationship between sampling rate and PWM frequency, and other factors.

 

The only way to answer definitively is to see some code.

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hwgeek1221 wrote:

 

I used the FFT feature on the oscilloscope to see them. In the figure I'm attaching you can see the time waveform in white and the FFT in purple (in the back).

 

Also note that when the LC filter is removed more sidebands near the 50Hz are observed having lower amplitudes and frequencies farther from 50 Hz.

 

Hmm. with no feedback loop anywhere, that certainly is strange.

To get this effect, you would need to shift that Sine-read slowly over 10 mains cycles. (4000 readings)

 

Is there anything your MCU is doing, that repeats at 4000 20Khz Cycles ?

 

Does your MCU have a DAC ? - that could provide a quick way to check Sine-read issues ?

 

An alternative is to capture the 20kHz edges into an Array, and dump the 4000 samples into a spread sheet.

Also check the 20kHz itself is stable - is this using a RC osc, or a Crystal ?

Also check power supplies for any 5Hz ripple effects.

Last Edited: Sat. Nov 21, 2015 - 09:46 PM
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Yes, it is being amplitude modulated, and that produces the "sidebands" you see

What do you think can cause such a modulation?

 

The waveform, itself, looks distorted at first, but that is  due  to the low sample rate and can be ignored for now. I am suspicious of that negative  spike about 6.5 divisions from the trigger. 

Yes, the distortion can be ignored because if you set the time division to something smaller you will observe sinusoidal waves. As for the negative spike, thats because i don't have a super clean Vcc. It carries spikes that are affecting the output of the driver that drives the transistors.

 

First question: What does your filter look like and what is its corner frequency

 It's a simple LC filter that acts as a LPF where the output voltage is measured across the capacitor. It has a corner frequency of about 3.5Khz

 

Second question: Look at the input  to your filter. Is the PWM signal constant amplitude? If it is, then you are looking at something that is  modulating the PWM process, itself

I didn't really understand this one. Did you mean that if it does not have a constant amplitude then i have modulation in the PWM process?

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Take a look at the VOLTAGE amplitude that is at the output of your switcher. IF that is steady, then something is happening at the software level. 

 

If it is software, it probably what Joey suggests, having to do with a "beat" between two different sample rates. 

 

All that said, your statement about the frequency components shifting when you remove the filter is a bit puzzling. I have not yet wrapped my head around that. But, first things first. What do the "logic levels" of the switcher output look like? Steady or not steady?

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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I'd look for jitter using diagnostic pulses on unused output  pins, e.g. one every lookup cycle and another every second.

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Jitter should appear random. This is VERY systematic. I suspect a problem with timing, but not in the jitter sense.Jitter might arise from interrupt latency, for example. This is not an example of latency jitter, quite sure.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Sun. Nov 22, 2015 - 03:49 PM
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All that said, your statement about the frequency components shifting when you remove the filter is a bit puzzling. I have not yet wrapped my head around that.

I took a few pictures of how it looks without the LC filter. As you can see there are multiple components next to the fundamental (50Hz) where some of which disappear after putting the LC filter and observing the voltage across the capacitor. As you can see there are similar components around the 3rd harmonics and the 5th. Does this alarm something?

 

Take a look at the VOLTAGE amplitude that is at the output of your switcher.

What do you mean by the switcher? Do you mean the signals that are triggering the gates of the transistors?

 

So the PWM clock will be  62.5 kHz.  Not 20 kHz.  If you're updating the compare match registers at a rate which is not a multiple of the PWM clock, you will see artefacts.  The nature of the artefacts you will see will depend upon the relationship between sampling rate and PWM frequency, and other factors.

I doubled check the frequency of the PWM clock and it is indeed 20 kHz. It is in up-down count mode.

 

Is there anything specific that you want me to make clear so that you can gain more insight into the system that i have? 

 

Edit: When I changed my switching frequency from 20kHz to 10kHz (keeping the modulated signal @50Hz) to test things out, i found that the gap between the frequency components expanded. That is, there was a fundamental component around 50Hz and next to it there were components on 42Hz and 58Hz (instead of 44 and 56 for the 20kHz case) and next to them other frequency components however they were farther than what was observed in the 20kHz case.

 

In addition, I also tried to change the fundamental frequency to 80Hz @ a switching frequency of 20kHz (250 points in lookup table) and the same phenomena appeared there too (fundamental at 80Hz and sidebands starting at 74Hz and 86Hz; note the 6Hz is common for the switching frequency @20kHz)

Last Edited: Thu. Dec 10, 2015 - 02:59 PM
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I doubled check the frequency of the PWM clock and it is indeed 20 kHz. It is in up-down count mode.

Huh?  I still don't see how you're getting 20 kHz.  If you're using dual slope mode, the frequency of an 8-bit timer will be F_CPU / (prescaler * 510).  With an F_CPU of 16 MHz, and no prescaler, that's 31.373 kHz.  To get 20 kHz, you'd need either a system clock of 10.2 MHz, or you'd need to use a timer prescaler and a TOP of < 255.  With a prescaler of 8, a TOP of 50 would get you 20 kHz.  But that would reduce the PWM resolution from 8 bits to about 5.5 bits.  That would compound the quantisation and phase noise that is almost certainly at the heart of what you are already seeing.

 

Is there anything specific that you want me to make clear so that you can gain more insight into the system that i have?

Yes.  Post your code and schematic.  I know you said:

Sorry I can't post the code neither the schematics because I don't have the soft version of the schematic and the console that im working on is not connected to the internet.

... but that's a weak excuse.  Take a digital photo of the schematic, and stick a USB thumb drive into your development system and make a copy of the code.  Otherwise you will get nothing but fuzzy crystal ball guesses.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

Last Edited: Wed. Nov 25, 2015 - 08:36 PM
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Huh?  I still don't see how you're getting 20 kHz.  If you're using dual slope mode, the frequency of an 8-bit timer will be F_CPU / (prescaler * 510).  With an F_CPU of 16 MHz, and no prescaler, that's 31.373 kHz

I've got a confession to make. I posted in the wrong section. I'm not using an 8-bit uC. It's a 32-bit cortex M3 with 12 bit PWM resolution. I thought that this won't make a much difference since this is a generic topic.

But believe me I have a PWM frequency of 20kHz.

 

I can write a very rough pseudocode for the modulation as I don't have access to the code. It's not that easy to get the code out. Note that I have unipolar switching where a positive symmetric triangular wave is compared to +sin and -sin waves.

 

Last Edited: Thu. Dec 10, 2015 - 03:00 PM
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hwgeek1221 wrote:

I've got a confession to make. I posted in the wrong section. I'm not using an 8-bit uC. It's a 32-bit cortex M3 with 12 bit PWM resolution.

What part code ?  Does this M3 have a DAC you can output the table info on ?

You really need to be sure the Sine info, actually is sine info when played back.

How does this M3 derive the SysCLK ? (tho this is way to large to be a subtle issue)

 

//Contains a 400 points of 5*sin(2*pi*50*t);

Err ?  5 * sin () ?

 

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Well, I can't help you with an ARM.

 

It sure would have been nice to have gotten answers to the questions you were asked days ago, like all the ones I asked you in post #9:

  • What speed are you running the AVR?  What is the exact timer config?
  • Are you using an interrupt to update the compare registers from a lookup of the sine table?
  • You haven't given enough information, but let's make some assumptions:
    • ATmega at 16 MHz cpu clock
    • TIMER1 running with no prescaler
    • 8-bit PWM

Twenty-questions is a boring game, unless I've got a Martini in one hand.

 

 

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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Looking at those pictures, I am not sure I would call that "PWM". Well maybe more than "not sure". Can you state what your algorithm is?

 

On top of that, the tops (and bottoms) of the pulses do not appear to be all the same amplitude. Maybe this is an optical illusion due to the oblique angle of the camera shot. 

 

I also do not understand the role of the bipolar pulses. I would expect nothing at the zero crossing of the 50Hz output, then pulses starting at a low duty cycle, increasing in duty cycle (but just one polarity) to the peak of the output, then decreasing in duty cycle to the next zero crossing,l then repeating, but with negative going pulses to the next zero crossing, then repeating, period by period (of the 50Hz output). I don't understand what you seem to be showing.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Sorry for not replying soon to all the questions that you made.

 

  • What speed are you running the AVR?  What is the exact timer config?
  • Are you using an interrupt to update the compare registers from a lookup of the sine table?
  • You haven't given enough information, but let's make some assumptions:
    • ATmega at 16 MHz cpu clock
    • TIMER1 running with no prescaler
    • 8-bit PWM

 

Unipolar PWM modulation is used as the switching scheme with an intended switching frequency of 20Khz. The uC is driven by an external 8MHz crystal oscillator and internal circuitry is used to do obtain a system clock of 168MHz. Timer 1 in PWM mode 1 running in up-down count mode is used to produce the outputs necessary to drive the transistors. Timer 1's advanced features such as complementary outputs and deadtime (600ns) are utilized to generate the signals to drive the transistors. The timer also runs on the same speed as that of the system clock (168MHz). TIMER_PERIOD = 4200 where timer goes 0->4200->0. Since each tick is (1/168E6), then 20KHz is achieved. PWM mode 1 sets the output to HIGH state when compare _value >= timer_counter.

The timer interrupt is entered on an overflow/underflow, however the outputs driving the transistors are updated only on an overflow event. A sin lookup table made of 400 points (50 us * 400 = 20 ms = 1/50Hz) cover a whole sin cycle of 50Hz with unity amplitude. On every overflow interrupt a new point from this sin table is obtained and is used to update the compare values as following:

 

CMPR1 = TIMER_PERIOD/2 + amplitude_required*sin_table[counter]*(TIMER_PERIOD/VDC);
CMPR2 = TIMER_PERIOD/2 - amplitude_required*sin_table[counter]*(TIMER_PERIOD/VDC);
counter = (counter + 1)%400;

The switching frequency was also observed to be 20KHz on the output of all the pins of the uC and on the input of the gates of the transistors. I would also add to this that the sin wave lookup table was obtained using MATLAB. The following statement basically fills up an array of size 400 that contains sin wave points separated by 50 us. 

sin_table =sin(2*pi*50*(0:399)*50E-6)

 To add on that, placing a constant value of lets say 1050 (=4200/4) in the CMPR1 value results in a 20KHz square wave signal with 75% and 25% duty cycle on the ppm outputs (normal and complementary). When placing 1050 on both CMPR1 and CMPR2 a voltage value of 0 is observed on the output of the LC.

 

Looking at those pictures, I am not sure I would call that "PWM". Well maybe more than "not sure". Can you state what your algorithm is?

 

On top of that, the tops (and bottoms) of the pulses do not appear to be all the same amplitude. Maybe this is an optical illusion due to the oblique angle of the camera shot. 

 

I also do not understand the role of the bipolar pulses. I would expect nothing at the zero crossing of the 50Hz output, then pulses starting at a low duty cycle, increasing in duty cycle (but just one polarity) to the peak of the output, then decreasing in duty cycle to the next zero crossing,l then repeating, but with negative going pulses to the next zero crossing, then repeating, period by period (of the 50Hz output). I don't understand what you seem to be showing.

I'm running unipolar PWM as I stated a couple of lines above.

I think we're not able to see things as we should because of the low sampling rate on the oscilloscope when the time scale get is in the range of ms.

 

Thank you for your feedbacks!

Last Edited: Sun. Feb 21, 2016 - 01:59 AM
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Use a logic analyzer on the pwm logic signal, measure timings, sort it out.

It all starts with a mental vision.