"Protecting" programming pins? (ISP)

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I've just had an Atmega fail on me, with the reset line going low impedance (and causing the device to stay in reset, rather than run)

 

I was updating the devices program with ISP, using an AVRISP Mk2, and although it accepted the new firmware, (ie it could be programmed, verified etc) the micro would just sit in reset and not execute the code!

 

I guess, that somehow i "zapped" the reset line when plugging in the ISP header (no, i wasn't wearing an antistatic wrist strap etc DOH!)?

 

So, does anyone "protect" those lines (reset, MISO, MOSI, SCK etc) using resistors or TVS etc between the ISP header and the micro?

 

Considering i much have programmed devices in this fashion literally thousands of times without issue since i started using AVRs 10 years ago, i guess it's not  really a big issue, and perhaps i was just unlucky this time?

 

Anyone else bricked a micro in this way??

 

indecision

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The RESET pin is vulnerable on those devices that implement 'high voltage' programming. Most pins have protective diodes, to ground and to V+. The RESET line in HV programmable devices do not have a protective diode to V+.

In the ATMEL application note AVR042, section 2 mentions that you should install an ESD protection diode if you do not plan to use HV programming... http://www.atmel.com/images/atmel-2521-avr-hardware-design-considerations_applicationnote_avr042.pdf

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And yeah, I think many of us have zapped a chip that way : }

 

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The next question, of course, is did you mess with the Fuses when you were programming the micro?

(i.e., Are you sure you zapped the chip?)

 

And, for the record, yes, I've zapped a chip a time or two, and an LCD on one PCB is now missing a row of pixels...

 

I don't usually wear a strap unless I am working with an expensive chip, or working on someone else's hardware.

 

That said, I am constantly touching a Ground to make sure I won't zap anything, (usually!).

 

JC

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Are you sure it is not just the fuses that got screwed up? If you are unsure then use a high voltage programmer and see if the chip responds.

 

As far as 8 bit uCs go, I have used the silabs 8051, microchip stuff, AVR stuff, cypress PSOC1 stuff. I find AVR is about average in terms of robustness to ESD and general stupidity, microchip stuff I have never ever blown one up, Cypress stuff I have blown up lots but that is mostly because cypress makes wacky complicated stuff, the silabs 8051 I have never blown up but I only used it for about 6 months where as the rest I have used for 2 or more years.

 

If this is a production product, you are better off just wearing a wrist strap and write up some protocol for handing electronics during the programming stage. Alternatively if you want rock solid protection then you have to put over current and over voltage protection on the product itself, which is a waste of components when proper ESD handing will do the same job.

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max_torque_2008 wrote:
So, does anyone "protect" those lines (reset, MISO, MOSI, SCK etc) using resistors ...
and a capacitor (low pass T-filter) to increase the rise/fall-time of the ESD/EFT/lightning (EOS) pulse; this reduces the energy into the AVR's EOS protection.
First RC is approximate to the EOS duration (roughly 100ns) (ref.).
Most AVRs have a Schmitt-trigger input to square-up (restore fast rise/fall-time) the signals so shouldn't affect the ISP function.

max_torque_2008 wrote:
... or TVS etc between the ...
And some resistors to reduce TVS current and current divide between TVS and AVR.
Several kinds of TVS with varying clamp methods, voltages, and currents.

max_torque_2008 wrote:
Considering i much have programmed devices in this fashion literally thousands of times ...
Yea, that's common and works well.
Otherwise, it's use the AVRISP to burn a bootloader then proceed with the loader-bootloader combination.

max_torque_2008 wrote:
... and perhaps i was just unlucky this time?
Apparently so.
There's a plethora of EOS methods.
A cell phone is a 2 watt transmitter and can destroy electronics.
The EMP from a nearby ESD event (iow not a direct strike).
Have experienced destruction of electronics and a possible non-destructive latch-up due to the EMP from a nearby lightning strike.
Have had to go through re-training on ESD prevention after proven destruction of a CMOS gate due to ESD (an expensive lesson learned).


Reference :

http://www.cambridge.org/us/academic/subjects/physics/electronics-physicists/art-electronics-3rd-edition?format=HB

12.1 CMOS and TTL logic interfacing
12.1.5 Input protection
(pages 804, 805)

"Dare to be naïve." - Buckminster Fuller