Hi,
i'm making a servo motor controller using ATMega8-16pi running at 16Mhz. I programmed it to produce a pulse at 1.5ms high and around 20ms low. The servo motor should be turned into its center position. But the fact is, it turned into the leftmost position. After i checked using oscilloscope, i probed the pin (without the servo) the pulse output is correctly measured 1.5ms as it is should be. but when the servo connected into the microcontroller, strangely the pulse signal is around 23ms high and 23ms low :shock: . I've tried with another servo motor (i got 4 servos) and they all showed same strange behaviour :? . Can anyone tell me what's wrong :?:
please note that the supply line is clean, i've added bypass cap to reduce noise from servo motor. the servo tipe is futaba s3003
here is the code:
.include "m8def.inc"
.def tmp =r16
.def tmp1=r17
.def rserv1 =r18
.def rserv_1 =r19
.def rserv2 =r20
.def rserv_2 =r21
.equ servo1 =0
.equ servo2 =1
.cseg
.org 0
rjmp start
.org 8
rjmp pwm
start:
ldi tmp,low(RAMEND) ;set stacks
out SPL,tmp
ldi tmp,high(RAMEND)
out SPH,tmp
ldi tmp1,0xff ;setup ports
out DDRC,tmp1
out PORTC,tmp1
rcall init_timer1
ldi rserv1,15 ;initiate servo pulse
ldi rserv_1,15
ldi rserv2,20
ldi rserv_2,20
ulang:
rjmp ulang
init_timer1: ;creating timer1 interrupt
ldi tmp,0xfa ;every 100us
out TCNT1H,tmp
ldi tmp,0x38
out TCNT1L,tmp
ldi tmp,0x00
out TCCR1A,tmp ;mode normal
ldi tmp,0x01
out TCCR1B,tmp ;clock prescale=1
ldi tmp,0x04
out TIMSK,tmp ;overflow interrupt
sei ;enable interrupt
ret
pwm:
cli ;disable interrupt
ldi tmp,0xfa
out TCNT1H,tmp ;reload
ldi tmp,0x38
out TCNT1L,tmp ;value
dec rserv1 ;decrease servo value
brne pwm1 ;if not zero then get the hell out
sbic PINC,servo1 ;
cbi PORTC,servo1 ;these commands is used
sbis PINC,servo1 ;to make a bit complement algorithm
sbi PORTC,servo1 ;
ldi rserv1,0 ;reload the low pulse
sbic PINC,servo1
mov rserv1,rserv_1 ;reload the high pulse
pwm1:
dec rserv2
brne done
sbic PINC,servo2
cbi PORTC,servo2
sbis PINC,servo2
sbi PORTC,servo2
ldi rserv2,20
sbic PINC,servo2
mov rserv2,rserv_2
done:
sei
reti
longdelay: ;this delays around 1s
ldi r20,80
d1:
ldi r21,0
d2:
ldi r22,0
d3:
dec r22
brne d3
dec r21
brne d2
dec r20
brne d1
ret