Mega part with NCO?

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Are there any Mega or Xmega parts with a built-in numerically controlled oscillator NCO (along the lines of Microchip 16F devices).  I need to generate various approx 75KHz square waves with tight freq adjusting resolution of a few Hz.  Using a timer divider does not cut it, since the step size is huge.  I need to step in much smaller steps.

 

I took a look at the parts & did not see any, but perhaps I overlooked something.

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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Have you had a look at Jesper's Mini-DDS?

IIRC he obtained 0.07 Hz resolution with an output freq of 200 Hz - 300 kHz.

With the DDS technique you can output a square wave, sin , triangle, saw tooth, EKG, etc.  Any repetitive waveform you desire.

 

JC

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No XMega/Mega/Tiny has a hardware NCO. As JC just pointed out, you don't need one using a software DDS (which is really a soft-NCO inside).

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Is there any further info/explanation on this approach?  I see some posts mentioning a website that is apparently defunct.

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Sun. Sep 6, 2015 - 03:43 AM
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avrcandies wrote:

Is there any further info/explanation on this approach?  I see some posts mentioning a website that is apparently defunct.

 

NCO has a native digital time-quantize of the adder time, and needs special attention to reach the Numeric LSB.

You need an Analog Sine, good LPF, and a slicing comparator that uses the whole cycle average to determine the zero crossing.

That means higher speed SW NCO works best on a fast AVR core, with a DAC.

I think the XMega's mostly fit that spec.

 

What Step Size and precision do you need & what cycle-to-cycle jitter can you tolerate ?

 

Another approach is to use the Oscillator Trim abilities, on AVRs that have that.

 

avrcandies wrote:

approx 75KHz square waves with tight freq adjusting resolution of a few Hz.

How many is a few Hz ?

Running some numbers :  On a XMega, with a 1MSps DAC that will limit the Adder speed, and at that 1MSps, you have just 13.333' cycles for a 75kHz Sine, so you need all the Y-Axis precision you can buy.

 

If you seek one part in 75k, that is ~ 13ppm, and past most Analog precisions/noise floors.

 

 

ie a full 12bit Sine LUT will give you 1 in 4096 Quanta on the Y-Axis, and one part of 4096 in 75k is 18Hz

With a good LPF,  you maybe could improve that by perhaps a factor of 10, to ~ 2Hz

 

All this means you may be better off with a Real Synthesis device, either HW DDS ($$), or clock generator since you want square waves..

 

eg Si5351A is not expensive (~ $1/100) and has high frequency PLL loops and can do 2kHz~200MHz

Mouser have an AdaFruit board for sub $10, with Xtal+Si5351A mounted.

A part like this allows you to choose almost any MCU.

 

Another choice is Si504, which takes a simple 32b float to set (almost any) frequency, but those are NRND.

 

Keep in mind that SW DDS will consume most of your CPU cycles, some miniDDS examples assume that is ALL the CPU is doing.

Last Edited: Sun. Sep 6, 2015 - 05:16 AM
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Simply scroll back to the top of this page and note the oval search box in the upper-right corner.

 

1. Type in miniDDS

2. Press <ENTER>

3. Much will be revealed.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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avrcandies wrote:

 I need to generate various approx 75KHz square waves with tight freq adjusting resolution of a few Hz.

 

Because SW DDS looks to struggle with that spec, I ran some numbers on my Si5351A suggestion

I asked for 3 outputs (since that is what it can do)  of

75.000 kHz

75.001 kHz

75.002 kHz

 

Report is below : ( claims 0.0ppm on all 3 )

& similar 0.0ppm errors report for 70.003 70.004 70.005 triple too.

PLL A
 Input Frequency (MHz) = 25.000000000
 VCO Frequency (MHz) =  700.000000000
 Feedback Divider = 28
 SSC disabled

PLL B
 Input Frequency (MHz) = 25.000000000
 VCO Frequency (MHz) =  799.702848000
 Feedback Divider = 31  385982/390625

Output Clocks
Channel 0
 Output Frequency (MHz) = 0.070002000
 Multisynth Output Frequency (MHz) = 0.560016000
 Multisynth Divider = 1428
 R Divider = 8
 PLL source = PLLB
 Initial phase offset (ns) = 0.000
 Powered down = No
 Inverted = No
 Drive Strength = b11
 Disable State = Low
 Clock Source = b11
Channel 1
 Output Frequency (MHz) = 0.070000000
 Multisynth Output Frequency (MHz) = 0.560000000
 Multisynth Divider = 1250
 R Divider = 8
 PLL source = PLLA
 Initial phase offset (ns) = 0.000
 Powered down = No
 Inverted = No
 Drive Strength = b11
 Disable State = Low
 Clock Source = b11
Channel 2
 Output Frequency (MHz) = 0.070001000
 Multisynth Output Frequency (MHz) = 0.560008000
 Multisynth Divider = 1428  1428/70001
 R Divider = 8
 PLL source = PLLB
 Initial phase offset (ns) = 0.000
 Powered down = No
 Inverted = No
 Drive Strength = b11
 Disable State = Low
 Clock Source = b11

 

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There will be no dac or analog output (I hope). I just need a 50% square wave.  need to adjust the freq in 10 Hz steps

 

The links for minidds  all seem defunct

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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Here is my version of Jesper's Mini DDS:

 

http://webspace.webring.com/peop...

Leon Heller G1HSM

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avrcandies wrote:

There will be no dac or analog output (I hope). I just need a 50% square wave.  need to adjust the freq in 10 Hz steps

 

That 'hope' depends on how much jitter per cycle you can tolerate.

 

What is the 75Khz used for / driving ?

 

If you remove the {DAC+LPF+Slicer} then any Digital DDS has a per-cycle jitter of the adder loop delay, it gets the apparent high precision by dithering over many cycles.

A frequency counter with a 100ms or 1s average time, will show good granularity, but a cycle by cycle read will be cosrse granulated.

 

example: A 16MHz DDS with a 9 SysClk Adder loop, ( & doing nothing else at all) can output  77294.685990Hz and 74074.07407407 Hz.  ( 562.5ns  edge placement, if you prefer)

It can average 75.00kHz or 75.01kHz etc by choosing a long term average ratio of those two values.

 

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Here is my version of Jesper's Mini DDS:

A very recent thread:

https://www.avrfreaks.net/forum/g...

 

where Cliff gave a link to an archive version, as well as discussion of DDS chips and similar.

 

Now, that poster had more modest frequency requirements.  In my head, if you use an AVR8 model with PLL that gives 64MHz PWM clock.  The minimum steps would then be close to OP's desires, right?

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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The links from an AVRFreaks search are all good.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Thanks for all of the useful updates!

 

If you remove the {DAC+LPF+Slicer} ....I should be able to remove the dac since the table for a square wave is all 0 or ff.  I'm just taking the MSB (r31==>portd, pd7) as my output.  I do see the timing jitter.  But applying filtering to remove it would not make a pretty square wave.

 

Since this is a servo loop app, the changes in freq must not be garbled by changing the 3 registers (smooth  freq updates).   Of course then you can't change the 3 freq setting registers will nilly.   Uart control can't interrupt the servo waveform either. 

 

So maybe put the nco in a fast interrupt, and just monitor uart in main..  Update the 3 freq control registers "carefully" (maybe make 3 shadow registers that get swapped over in the interrupt).

 

What is this 'slicer', I  just saw some d/a's & filters in the projects...did I overlook it?

 

I wonder why AVR has no NCO, it's a shame to put so much work on the  processor (burns up a lot of %)

 

Which parts can run faster than 20MHz  (does it have to be xmega?) If the cpu speed goes up, things get easier.

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Sun. Sep 6, 2015 - 05:02 PM
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You can remove the portion of the jitter contributed by the interrupts by not using them for the output directly.  Instead, use an output compare pin on a timer and use the interrupt to schedule the next compare match.

 

You will of course still incur the jitter inherent in the underlying DDS algorithm.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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avrcandies wrote:

Thanks for all of the useful updates!

 

If you remove the {DAC+LPF+Slicer} ....I should be able to remove the dac since the table for a square wave is all 0 or ff.  I'm just taking the MSB (r31==>portd, pd7) as my output.  I do see the timing jitter.  But applying filtering to remove it would not make a pretty square wave.

...

What is this 'slicer', I  just saw some d/a's & filters in the projects...did I overlook it?

 

The slicer is a Comparator, and yes, the LPF output is a Sine Wave, not square.

The problem is the Time-Domain Edge resolution. 

A Digital only approach, ( remove the {DAC+LPF+Slicer}) can only define any edge to LoopCycles/SysCLK  ns  (562ns above)

 

If you seek 10Hz LSB, and want that in a Single cycle, you need to place any edge to

 1/75k - 1/75.01k = 1.77754 ns  - see the difference ?

 

What the LPF does is use the Y axis (voltage information from DAC) to give better time precision, and it integrates many points to give that sine. The Slope at Zero crossing is what gives the improvement in time precision.

 

 

avrcandies wrote:

Since this is a servo loop app...

 

Again, the question is what edge jitter can that tolerate ?

 

How does it measure the frequency/period to resolve these 10Hz changes you feed it ?

Does it time over XX cycles ? With what SysCLK ?

What is the servo response time ?

 

 

avrcandies wrote:
If the cpu speed goes up, things get easier.

Only modestly, until you get to 562.575MHz, which allows you to get 10Hz precision within a single cycle, with a simple /N

 

You may be able to move the jitter-spread to less than what the servo can notice, but until we know what that is, who can say.

 

Last Edited: Sun. Sep 6, 2015 - 07:46 PM
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How does it measure the frequency/period to resolve these 10Hz changes you feed it ?

Does it time over XX cycles ? With what SysCLK ?

What is the servo response time ?

 

Those are all good questions...I suspect that present jitter might be tolerable (it directly drives an analog sensor), but would have to try in actual application.  Right now have it blazing along in main code, but would have to move to fast repetition isr to allow use of uart  without disturbing waveform.  Also need to adjust the freq without big disturbances in the output.

 

I wonder why AVR has no NCO option, seems easy & would take a big load off the processor. 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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avrcandies wrote:
I wonder why AVR has no NCO option
I wonder why my wristwatch can't make me a hamburger.

 

There is no AVR with an NCO because Atmel haven't made one.  They haven't made one because they haven't identified a market opportunity for one, and no client has approached them with a good business case.  If you want an AVR with integrated NCO, approach Atmel with your specifications, the quantity you're looking for, and how much you're prepared to pay for them.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

Last Edited: Sun. Sep 6, 2015 - 08:14 PM
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and how much you're prepared to pay for them...

 

Wimpy is Popeye's friend. Hamburgers are Wimpy's all-time favorite food, however he is usually too cheap to pay for them himself.  His best-known catchphrase started in 1931 as "Cook me up a hamburger. I'll pay you Thursday.

Maybe Atmel would trade Chips for Hamburgers. 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Sun. Sep 6, 2015 - 09:14 PM
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Mega's run at 16 MHz, and 20 MHz, Xmega's run at 32 MHz.

 

If this is a commercial product, stick with the 32 MHz.

 

If this is a one-off for your own use you can generally overclock the Xmega, at least to 48 MHz, (if not using the EEPROM, or analog portions of the uC).

 

The Xmega's also have a priority interrupt controller, so the DDS ISR can have the highest priority, and the USART can run at the Medium Level priority.

 

JC

 

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If you're going to go down the xmega route, there might be a more precise approach. Xmegas have an option of generating the system clock using a 1.024kHz reference (which can be an internal RC oscillator or an external 32kHz watch crystal) driving an FLL frequency multiplier. I haven't checked to make sure this actually works, but I suspect a system clock of around 38.4MHz, and a clock divider of 512, you should be able to get clock steps of around 2Hz for a clock output of around 75kHz.

 

Note that in this setup, changing clock output frequencies will be messy - you need to temporarily change the system clock away from the FLL when you change the FLL multiplier.

 

- S

 

Last Edited: Mon. Sep 7, 2015 - 04:20 AM
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mnehpets wrote:

 I haven't checked to make sure this actually works, but I suspect a system clock of around 38.4MHz, and a clock divider of 512, you should be able to get clock steps of around 2Hz for a clock output of around 75kHz.

?  - I make one part in 512 of 75k,  ~146.5Hz , not 2Hz.

 

You may have meant a COMP[15:0] value of 37500, which gives one part in 37500, which is ~2Hz averaged over many of the 73,24 Cycles of 75kHz that the samples update at.

 

However,  note that is a long term average, the Trim LSB of the XMegaE5 for example is ~ 0.2% so the FLL will choose a value that may be 150Hz high, ie 75.150k and run that for 1ms, then choose an adjacent 0.2% and run that, and update again 1ms later.  A 1ms modulation on a servo loop, may not be such a good idea ?

 

It is a pity Atmel did not think to allow users to choose that FLL refresh rate.

 

Another choice may be the SAMD10 - which mentions

Fractional Digital Phase Locked Loop (FDPLL96M)
# 48MHz to 96MHz output clock frequency
# 32KHz to 2MHz input reference clock frequency range
# Three possible sources for the reference clock
# Adjustable proportional integral controller
# Fractional part used to achieve 1/16th of reference clock step

 

Which yields a ~ 3.7Hz Step size, ( not sure of the dither grouping, data is vague there....)

 96M/1280 = 75000

 96M/(1280-1/16) = 75003.662

- and that with close to zero run-time SW overhead

 

 

 

 

 

Last Edited: Mon. Sep 7, 2015 - 05:31 AM
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avrcandies wrote:

 I just need a 50% square wave. [75kHz]  need to adjust the freq in 10 Hz steps

 

Another approach to this need for 75kHz, 10Hz steps that avoids needing high oscillator values, is to flip to the analog domain.

 

eg A device like TS3006 is a Resistor Controller Oscillator

www.digikey.com/product-detail/e...

* 9kHz ≤ FOUT ≤ 300kHz
* Single Resistor Sets Output Frequency
* FOUT Period Accuracy: 3%
* FOUT Period Drift: 0.02%/ºC

* FOUT Jitter  0.001  %

* FOUT Period Line Regulation  Δt FOUT /V  (1.55V ≤ V DD ≤ 5.25V)  ~0.17  %/V

 

10Hz step in 75kHz is 0.013%

 

Such a device could be frequency swept from a DAC pin, and Frequency calibrated against the MCU clock.

 

Last Edited: Tue. Sep 8, 2015 - 12:30 AM
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Silly question but if a 16F has the NCO you want why not use a 16F?

 

(OK, I know, I know, sacrilege and all that, but why cut off your nose to spite your face?)

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clawson wrote:

Silly question but if a 16F has the NCO you want why not use a 16F?

 

I'm also curious what the OP decided to use.

 

The PIC NCO does have limits - with a 16Mhz clock, it gives  a dT quanta of 62.5ns, an idealized divide of

 16M/75k = 213.333333333333333

So the edge placement  behaves like a mix of  two frequencies, that averages over time.

16M/213 = 75117.3708920187793

and

16M/214 = 74766.3551401869159

 

The LSB is 15.256Hz

 

A 32MHz AVR Modulated timer design, is going to have less LSB jitter than a 16MHz PIC NCO, but the PIC NCO does have a set-and-forget simplicity to it.