AVR Freaks

A quick google landed me at an Atmel page that had the settings and a quick rundown.

 Link?  I kept ending up on UC3 pages, which didn't match the D10 at all.  (and the ASF documentation that said "system_clock_init() sets up the clocks as per conf_clocks.h" without describing the conf_clocks.h format.

this has nothing whatsoever to do with ARM - it is entirely Atmel stuff

Perhaps.  But the complexity seems to be common to ARM chips from many different vendors, not just Atmel.

At the moment, I'm trying to figure out why there are both FLL and PLL clock sources in the same chip.  They seem to do about the same thing and have similar input and output requirements, and neither one provides a very generalized frequency multiplier.  (FLL has output frequency of 48MHz.  PLL has output frequency of 48 to 96MHz.)   Is the FLL particularly low-power compared to the PLL?  I couldn't find a number for it in the datasheet.  Does the PLL offer many frequencies up to 48MHz by permitting fractional multipliers yielding 48-96MHz, which then get divided by prescalers to yield the system clock?  (ie if I want 32 MHz given an 8MHz clock input, I'd divide by 8 (=1MHz), multiply by 64, and then divide by 2?  (huh.  Didn't even require fractions...))

No "perhaps" - it is for sure!

I'm still not sure I'm convinced.  ARM gets to defined "The CPU and the Bus controller and the memory and the peripherals all have different clock inputs", the the actual chip manufacturers feel compelled to make them be individually configurable, whether or not it makes much sense (especially in a CM0-class chip.)  OTOH, I guess the original CM3 chips (Luminary micro) had really awful power consumption specs, so maybe the separate clocks WERE needed to help solve those issues.  (I never dove into those early chips deeply enough to notice whether they had similarly complex clock circuits...)

Does the PLL offer many frequencies up to 48MHz by permitting fractional multipliers yielding 48-96MHz, which then get divided by prescalers to yield the system clock?

 This seems to be the case.  Using conf_clocks.h and ASF, I got my LED blinking at a couple of intermediate rates (20Mz, 30MHz, 40MHz)...

Now to see if I can get the PLL working without ASF...

Well, here is my non-working attempt at a non-ASF PLL-based clock configuration.   As far as I can tell, it sets up the assorted sysctl registers the same as the ASF-based version (which DOES work.)

It hangs waiting for the PLL clock to be "good".   Any ideas what could be wrong?  It looks to me like the PLL should be slightly easier to use than the FLL, because the PLL can use the (divided) XOSC clock directly (via ...REF1), rather than needing to configure one of the generic clocks to use as an input.  Perhaps there is some other dependency that I'm missing?

void system_clock_init()
{
	//Enable the 8MHz oscillator input from SAMD10 XMini
	REG_SYSCTRL_XOSC = (SYSCTRL_XOSC_ENABLE);
	
	//Wait for the crystal oscillator to start up
	while((REG_SYSCTRL_PCLKSR & (SYSCTRL_PCLKSR_XOSCRDY)) == 0);
		
	//Set flash wait state to 1, which we need to do at 48MHz
	REG_NVMCTRL_CTRLB |= (NVMCTRL_CTRLB_RWS(1));
	
	//Configure the DPLL

	SYSCTRL->DPLLCTRLA.reg =
		(1UL << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) |
		(0UL << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos);

	SYSCTRL->DPLLRATIO.reg =
		SYSCTRL_DPLLRATIO_LDRFRAC(0) |
		SYSCTRL_DPLLRATIO_LDR(480);  /* Refclock will be 100kHz, this should give 48MHz */

	SYSCTRL->DPLLCTRLB.reg =
		SYSCTRL_DPLLCTRLB_DIV(39) /* Refclock divider */ | 
		SYSCTRL_DPLLCTRLB_REFCLK(SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC);

	SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE;
	
	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL))
	   /* HANGS HERE */;
	
	//For generic clock generator 0, select the DPLL Clock as input, divide by 2
	REG_GCLK_GENDIV = ((2 << GCLK_GENDIV_DIV_Pos) | (0 << GCLK_GENDIV_ID_Pos));
	REG_GCLK_GENCTRL = ((0 << GCLK_GENCTRL_ID_Pos) | (SYSTEM_CLOCK_SOURCE_DPLL) | (GCLK_GENCTRL_GENEN));
	REG_GCLK_CLKCTRL = ((GCLK_CLKCTRL_GEN_GCLK0) | (GCLK_CLKCTRL_CLKEN)) ;
}

SYSCTRL_DPLLCTRLB_REFCLK(SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC);

equates to (1 << 4), I don't have the SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC on my system ?

 It certainly seems to.  I guess I have a sort of mishmash of ASF and chip-level definitions in this code.   Something to clean up when it's working?

I end up with:

                        ASF     Bare metal
PLLCTRLA 0x80000844:   0x82     0x82
PLLRATIO 0x80000848:   0x1DF    0x1DE  (479 or 480, to muliply by 100kHz)
PLLCTRLB 0x8000084C:  0x270010  0x270010  (0x27 = 39, to get 100kHz from 8MHz)
PLLSTAT  0x80000850:   0xF      0x8 (not enabled, not ready, not locked :-( )
 --
 PCLKSR  0x8000080C   0xDA11    0x5819  (I don't have brownout enabled.)
 XOSSC   0x80000810   0xF882    0x2   (Hmm.  "2" is enabled.  All the rest is
                                       for the crystal stuff I'm not using.)

system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL)

Ends up doing:

		return ((SYSCTRL->DPLLSTATUS.reg &
				(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) ==
				(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK));

your board uses a crystal oscillator, and not just a crystal ?

Yep.  It's a SAMD10 Xplained Mini, so the meDBG chip provides an 8MHz clock to Xin.

Yes, that seems to take it beyond the clock initialization.

No blinking, though.  I suspect GPIO needs a clock.  (although, the working FLL code didn't give it one.  Perhaps it defaults to GENCLK1)

Ahh.  I seem to have problems with the "source" for GCLK0.

It seems that the project includes *two* version of gclk.h.

There is C:\Program Files\Atmel\Atmel Toolchain\ARM GCC\Native\4.8.1443\CMSIS_Atmel\Device\ATMEL\samd10\include\component\gclk.h

Which has clock source definitions that need to be shifted into place:

#define   GCLK_GENCTRL_SRC_XOSC32K_Val    0x5ul  /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
#define   GCLK_GENCTRL_SRC_OSC8M_Val      0x6ul  /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
#define   GCLK_GENCTRL_SRC_DFLL48M_Val    0x7ul  /**< \brief (GCLK_GENCTRL) DFLL48M output */
#define   GCLK_GENCTRL_SRC_FDPLL_Val      0x8ul  /**< \brief (GCLK_GENCTRL) FDPLL output */

And then there is C:\Documents and Settings\Bill\My Documents\Atmel Studio\D10-LED_TOGGLE0\D10-LED_TOGGLE0\src\ASF\sam0\utils\cmsis\samd10\include\component\gclk.h

Which has clock source definitions that have already been shifted into place (and doesn't include the PLL!):

#define GCLK_GENCTRL_SRC_OSC32K     (GCLK_GENCTRL_SRC_OSC32K_Val   << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_XOSC32K    (GCLK_GENCTRL_SRC_XOSC32K_Val  << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_OSC8M      (GCLK_GENCTRL_SRC_OSC8M_Val    << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_DFLL48M    (GCLK_GENCTRL_SRC_DFLL48M_Val  << GCLK_GENCTRL_SRC_Pos)

(Oh wait, there's a 3rd one: C:\Documents and Settings\Bill\My Documents\Atmel Studio\D10-LED_TOGGLE0\D10-LED_TOGGLE0\src\ASF\sam0\utils\cmsis\samd10\include\instance\gclk.h)

That's really... rather depressing.  I wonder which files are including which includes?

The fll code (included in the main program) seems to be getting its definition from the 2nd location (which doesn't have a PLL value.)

I am not having much luck substituting in known constants :-(

The datasheet keeps saying that the gclk can have an input source selected from 8 choices.  The PLL is the 9th. :-(  I'm not feeling warm and fuzzy.

I guess tomorrow I'll trace through the ASF code more carefully, and see what it does.

Current state-of-the-code (seems to be working for a broad (beyond spec!) range of F_CPU targets from 16MHz to 55MHz...

#define USEPLL 1
	#define F_CPU 30000000		/* Desired target frequency */
	#define EXTCLK_FREQ 8000000  /* External clock freq on SAMD10 Xplained mini */
	#define F_INTERM 32000		 /* Intermediate frequency.  <33KHz for FLL, <2MHz for PLL */

void system_clock_init()
{
#ifdef USEPLL
#define EXTCLK_DIV ((EXTCLK_FREQ/(2*F_INTERM)) - 1)
	//Enable the 8MHz oscillator input from SAMD10 XMini
	REG_SYSCTRL_XOSC = (SYSCTRL_XOSC_ENABLE);
	
	//Wait for the crystal oscillator to start up
	while((REG_SYSCTRL_PCLKSR & (SYSCTRL_PCLKSR_XOSCRDY)) == 0);
		
	//Set flash wait state to 1, which we need to do at 48MHz
	REG_NVMCTRL_CTRLB |= (NVMCTRL_CTRLB_RWS(1));
	
	//Configure the DPLL

	/*
	 * The output of DPLL is supposed to be between 48MHz and 96MHz.
	 * By setting the PLL output to 2*F_CPU, we have easy acess to
	 * most of the "interesting" frequencies between 24MHz and 48MHz
	 * Lower F_CPU can be obtained by increasing the GCLK0 divisor.
	 */
	SYSCTRL->DPLLRATIO.reg = SYSCTRL_DPLLRATIO_LDR(2*F_CPU/F_INTERM);
	SYSCTRL->DPLLCTRLB.reg = SYSCTRL_DPLLCTRLB_DIV(EXTCLK_DIV) | /* Refclock divider */
		SYSCTRL_DPLLCTRLB_REFCLK(SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC);
	SYSCTRL->DPLLCTRLA.reg = SYSCTRL_DPLLCTRLA_ENABLE;
	
	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL));

	//For generic clock generator 0, select the DPLL Clock as input, divide by 2
	REG_GCLK_GENDIV = ((2 << GCLK_GENDIV_DIV_Pos) | (0 << GCLK_GENDIV_ID_Pos));
	REG_GCLK_GENCTRL = ((0 << GCLK_GENCTRL_ID_Pos) | (8 << GCLK_GENCTRL_SRC_Pos)| (GCLK_GENCTRL_GENEN));
	REG_GCLK_CLKCTRL = ((GCLK_CLKCTRL_GEN_GCLK0) | (GCLK_CLKCTRL_CLKEN)) ;
#endif /* USEPLL */
}

Random observation:  Code that accesses a structure-like definition of peripheral registers via a base address, like:

	SYSCTRL->DPLLRATIO.reg = SYSCTRL_DPLLRATIO_LDR(2*F_CPU/F_INTERM);
	SYSCTRL->DPLLCTRLB.reg = SYSCTRL_DPLLCTRLB_DIV(EXTCLK_DIV) | /* Refclock divider */
	         SYSCTRL_DPLLCTRLB_REFCLK(SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC);
	SYSCTRL->DPLLCTRLA.reg = SYSCTRL_DPLLCTRLA_ENABLE;

Well end up slightly smaller than code that accesses the same registers individually, like:

    REG_SYSCTRL_DFLLCTRL = (SYSCTRL_DFLLCTRL_ENABLE); //Enable the DFLL
    REG_SYSCTRL_DFLLMUL = (SYSCTRL_DFLLMUL_CSTEP(5) | SYSCTRL_DFLLMUL_FSTEP(10));
    REG_SYSCTRL_DFLLMUL |= (SYSCTRL_DFLLMUL_MUL(48000000/(EXTCLK_FREQ/EXTCLK_DIV)));
    REG_SYSCTRL_DFLLCTRL |= (SYSCTRL_DFLLCTRL_MODE);

This is because the compiler doesn't seem to be quite smart enough to notice that one constant pointer reference is withing "indexing" range of a previous pointer reference, and will reload the pointer for each of the latter example's register, while only loading a pointer once for the first example.

Apparently not.   This is a result of code with both, compiled with -O3:

// (Note that R2 already has &SYSCTRL from previous statements.)
//
    SYSCTRL->DPLLRATIO.reg = SYSCTRL_DPLLRATIO_LDR(2*F_CPU/F_INTERM);
 2b6:	6490      	str	r0, [r2, #72]	; 0x48
    SYSCTRL->DPLLCTRLB.reg = SYSCTRL_DPLLCTRLB_DIV(EXTCLK_DIV) | /* Refclock divider */
 2b8:	64d1      	str	r1, [r2, #76]	; 0x4c
        SYSCTRL_DPLLCTRLB_REFCLK(SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC);
    SYSCTRL->DPLLCTRLA.reg = SYSCTRL_DPLLCTRLA_ENABLE;
 2ba:	5513      	strb	r3, [r2, r4]

;----------------------------------------------------

    REG_SYSCTRL_DPLLRATIO  = SYSCTRL_DPLLRATIO_LDR(2*F_CPU/F_INTERM);
 2bc:	4c0d      	ldr	r4, [pc, #52]	; (2f4 <system_clock_init+0x64>)
 2be:	6020      	str	r0, [r4, #0]
    REG_SYSCTRL_DPLLCTRLB = SYSCTRL_DPLLCTRLB_DIV(EXTCLK_DIV) | /* Refclock divider */
 2c0:	480d      	ldr	r0, [pc, #52]	; (2f8 <system_clock_init+0x68>)
 2c2:	6001      	str	r1, [r0, #0]
        SYSCTRL_DPLLCTRLB_REFCLK(SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC);
    REG_SYSCTRL_DPLLCTRLA = SYSCTRL_DPLLCTRLA_ENABLE;
 2c4:	490d      	ldr	r1, [pc, #52]	; (2fc <system_clock_init+0x6c>)
 2c6:	700b      	strb	r3, [r1, #0]
    

(The use of different registers for each loaded address in the 2nd case is "interesting."  I guess the register allocator is working harder than it really needs to.)

Edit:  the range of indexing off of a base register is "not very much" (0..124 for words, 0..31 for bytes), so larger peripherals may be "interesting."