Help me understand this SPI multi-slave setup & schematic

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I need to share SPI between EEPROM & Switch Input w/ 74HC165's. I found some sample code and schematic that works great but I don't fully understand it. Please refer to the schematic attached. 

 

1) I know from research the 74HC165's aren't SPI compliant and need to be tri-state to share the MISO line. In the circuit attached the slave select line on the 74HC165 is connected to ground so it's always enabled. It looks like the switch latch connection enables one of the tri-state buffers in the 74HC126 so that when the latch is pulsed the data from the 165 is connected to the MISO line. At the same time it looks like the EEPROM is disabled, so when the switch latching is happening the 165 is connected and when it's not happening the 165 is tri-stated and the EEPROM is enabled. Am I understanding this correctly?

 

2) There is another tri-state buffer connected to the RESET line, with the enable pin connected to 5V. I think it has something to do with softening the reset pulse if an external reset switch is used (it's similar to application note AVR042). I don't ever use a reset switch when I program via ISP w/ atmel studio 6. Do I need this bit of circuitry?

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Last Edited: Fri. Mar 20, 2015 - 08:31 PM
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When sw_latch is high you get the 165 data, when low, the eeprom. I agree, the reset circuit is a bit weird.

If you were not short of port pins, i would just run the 165 via bit-bashing (software spi) and have no need for the 126. I'd probably use a i2c eeprom.