attiny85 PLL: Use External VCO As Tracker?

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Hi

Regarding attiny85

Can I drive an external VCO with the PLL, to make the external VCO track an attiny internal oscillator?

I'm guessing this is the opposite of the normal configuration.

Thx!

Last Edited: Tue. Jan 6, 2015 - 05:37 AM
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If the ATtiny85 has an output for the multiplied clock, then just use that as the reference signal to the phase detector of you PLL. Use the filtered phase detector to control the VCO, and feed the VCO output back as the other phase detector input. However, looking at the system clock specs, it appears that the CLKO output with the PLL is ONLY the 64MHz clock divided by 4. So, strictly speaking, it does not appear that you have access to full  PLL frequency.

 

That said, the frequencies you would be working with are pretty high for phase detector inputs. We usually see reference signals in the KHz region. You MAY need a phase detector with a scaler on both the reference and feedback signals. I think that TI (ex-National Semi) parts may do this. Then, you can multiply the VCO to almost any frequency in an integer relationship to the internal 64MHz oscillator.

 

For example, use the 16MHz CLKO signal, divide that by 128 in a reference prescaler. Divide the VCO by 512. If everything is right, the external VCO will track the internal 64MHz quite precisely because the internal divide by 4 has a precise phase relationship to the internal 64MHz PLL signal.

 

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

Last Edited: Tue. Jan 6, 2015 - 06:19 AM
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it appears that the CLKO output with the PLL is ONLY the 64MHz clock divided by 4. So, strictly speaking, it does not appear that you have access to full  PLL frequency.

But OP mentioned "internal oscillator".  OP -- What frequency do you want?  Like 8MHz?  (i.e., the actual AVR clock speed) Then use CLKO.

 

I haven't done it, but can't you get clk/2 with a degenerate PWM (or CTC if it applies)?  That would bring it up to like 32MHz.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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theusch wrote:

I haven't done it, but can't you get clk/2 with a degenerate PWM (or CTC if it applies)?  That would bring it up to like 32MHz.

I've never done it either, but have always wondered if you could ever get an output to toggle faster than the I/O clock. I suppose since TIMER1 has an async mode the answer should be yes, but the proof is in the pudding.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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Sir,

       1.  I am novice to microcontroller.  i want to know how can i use attiny 85 interfacing with LMX2531 PLL (National semiconductor). I want to fix the register values in LMX 2531 by using programming of attiny 85.

please explain and send C code (program) . How can i use Clock , data, latch pins of PLL2531 with attiny 85.

Seeking your early response

2. Presently I am givng the refrence freq of 10 MHz externally to the PLL chip 2531. can it given using attiny 85 . how can i multiply the interclock using TI/national semicoductor mutipliers. please explain using a example and c code

Thanks

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Greetings:

 

1. Nobody will send you code. This is for you to start figuring out. Then, you will get plenty of help.

 

2. That device is totally inappropriate for your application. The lowest frequency the VCO will operate at is 550MHz. Other versions of that chip WILL operate down to 32MHz.

 

3. The interface is "microwire". It is like SPI, but a single data line. It is pretty challenging to make this work with a standard hardware SPI interface. It is arguably easier with a software ("bit-banged") interface. In either case, it would take a lot of learning. 

 

4. You can use the CLKO function of the Tiny85 to create a 16MHz reference for the PLL. 

 

Please, you have not told us enough about what you want to do. It is hard to help with such limited information. Please tell us more about what you are trying to create!

 

Best wishes

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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Nm

Last Edited: Fri. Jan 9, 2015 - 07:47 AM
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Did not notice it was two separate posters. Sorry for following the hijack.

 

Did the earlier responses help at all? 

 

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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No worries. Thanks to the peeps who responded to my question.

 

ka7ehk wrote:
the frequencies you would be working with are pretty high for phase detector inputs.
 

 

I don't care at all about frequency range. I don't care if it is or isn't divided. I just want to set the frequency of an internal oscillator with attiny85 firmware, and force an external VCO to track that oscillator. Sounds like you're saying I CAN do this, but would have a limited frequency range, or something?

 

Really appreciate the feedback, but all the talk of frequencies is confusing the issue. I'm familiar with using dividers to scale the frequencies etc, but that's not what i'm concerned with ATM. 

 

ka7ehk wrote:
You MAY need a phase detector with a scaler on both the reference and feedback signals.

Are you suggesting an external PLL? The '85 has an internal PLL-- I assume its internal osc is designed to work with it, no?

 

Ignoring issues of frequency range, scaling, etc-- just want to know if i can use an external VCO with the internal PLL. This other thread seems to say 'no'.

https://www.avrfreaks.net/forum/n...

 

Thx!

Last Edited: Fri. Jan 9, 2015 - 05:56 PM
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The only access to the PLL is its output, either by way of CLKO or OC1x. You have indirect control of the input frequency by way of OSCCAL. The phase detector, filter, and VCO connections are internal to the silicon and you have no physical or programatic access or control of them.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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Here are the simple facts:

 

1) Yes, there is an internal PLL.

 

2) When the PLL is used, the MCU clock is a divided version of the PLL output (divided down to 16MHz)

 

3) The clock output ONLY gives you access to the MCU clock, not the PLL clock

 

So.....

 

If you want to track 1:1 the internal PLL frequency, you will have to use some kind of frequency multiplying system. Does not have to be PLL but PLL may be the easiest. Note that, since the MCU clock is a divided version of the PLL output, the two track each other perfectly. Thus, multiplying the MCU clock back up by the same ratio that it was internally divided, you will have something that tracks the internal PLL frequency.

 

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

Last Edited: Fri. Jan 9, 2015 - 09:16 PM
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ka7ehk wrote:
If you want to track 1:1 the internal PLL frequency

 

Jim, i appreciate your attention to tracking the frequency 1:1, but again for my purpose the 1:1 is not crucial atm. Could be 5:1 or 1:12 etc, don't care for now. As long as it tracks somehow. 

 

  • PLL V to external device: The first goal is getting the PLL phase-comparator output (pre- or post-filter) to an external device.

 

I think i'm hearing that getting the PLL phase-comparator output (pre- or post-filter) to an external pin is impossible, no?

 

If impossible, then next question, can the MCU internally detect the phase-comparator output (pre- or post-filter)? 

 

thx!

Last Edited: Sat. Jan 10, 2015 - 12:15 AM
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The datasheet would tell you if you could access the phase comp output. Sadly, it says nothing of the sort. The pll may not even be implemented on the silicon how we might expect. This exact question has been asked before as the answer is still the same - no. You want to do pll magic? Use an external pll. Make sure you read the datasheet carefully - the AVR may not appreciate its clock changing.

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Kartman wrote:

The datasheet would tell you if you could access the phase comp output. ...The pll may not even be implemented on the silicon how we might expect.

 

yes, i have looked through the datasheet, but as a non-expert i look to more experienced and knowledgeable people to help me understand. 

 

also, as you point out, the PLL might be be implemented as we expect-- the datasheet does not tell us. Ie, the datasheet does not necessarily tell all.

 

But, you speak as an expert with complete knowledge. 

 

(i had forgotten about that older thread, which was for a different purpose.)

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Experienced and knowlegable people have read the datasheet! I'm sorry if my statement offended you as there was no malice on my part. You fired back with a sarcastic response. I've been referred to the datasheet many times and reminded of fundamental principles many times.

If you want to find out about the internals, ask Atmel. When you find out, tell us.
Us mortals rely on the datasheet. Sure, it's not the absolute last word, but its a good starting point.

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no worries, no offense. 

 

now i'm trying to understand the relationship between the PLL and the PWM output.... if there is one!

 

if there's a relationship between the PLL and the PWM output, then maybe i can use that to find out what's happening with the PLL. 

Last Edited: Sat. Jan 10, 2015 - 02:36 AM
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[posting from phone, apologies for no formatting] The only way I can think of to gain an understanding of the relationship between the PLL clock input and PLL clock output would be to fuse for the 8 MHz calibrated internal RC oscillator with CKOUT, and then programatically enable async mode for TIMER1 and set up OC1A to toggle with prescaler 1 and TOP=0. This should give you a 32 MHz output (PLL/2) which you can compare to CKOUT. In particular, OC1A will track CKOUT, but with the latency inherent to the phase comparator/filter/VCO (or whatever the PLL implementation internals are). You can change OSCCAL and see what happens. CKOUT should see a step change, but OC1A may 'ring' a bit before the PLL stabilises at the new frequency.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

Last Edited: Sat. Jan 10, 2015 - 03:34 AM
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Thx Joey. I think basically you're saying I can look at the ref oscillator and the VCO output, and thus gain understanding of the relationship.

I appreciate that, but not quite what I seek. Looking for something closer to the comparator output if possible.

Something I read someplace seemed to suggest a relationship between the PLL and pwm. Hoping that might be useful.....

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The ONLY relationship between the PLL and the PWM output is the size (duration) of one PWM time slot. The time slot is equal in duration to the period  of the timer's clock. Pure and simple.

 

The duty cycle of the PWM remains unchanged as its clock changes. Only the absolute period and on-times change, but remain in a fixed proportion depending ONLY on the OCR register value for that PWM output.

 

The fact that a PWM timer is clocked with a 32MHz or 64MHz PLL-generated clock or to an 8MHz or 16MHz non-PLL clock is basically irrelevant. The only thing that changes because of such clocking is the net PERIOD of the PWM signal.

 

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

Last Edited: Sat. Jan 10, 2015 - 04:00 AM
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[OK, I'm at a real keyboard now]

 

johnyradio wrote:
Thx Joey. I think basically you're saying I can look at the ref oscillator and the VCO output, and thus gain understanding of the relationship.
That is the only avenue available to you.

 

Quote:
I appreciate that, but not quite what I seek. Looking for something closer to the comparator output if possible.
Nope.

 

Quote:
Something I read someplace seemed to suggest a relationship between the PLL and pwm. Hoping that might be useful.....
When TIMER1 is clocked asynchronously by PCK, then PWM output from TIMER1 will be locked to the PLL (i.e. VCO) output.  That's why I suggest configuring TIMER1 to toggle OC1A.  Put a DSO channel onto OC1A, and another on CKOUT.  Do not fuse for the PLL as a system clock source.  Doing so will result in CKOUT and OC1A staying in lock step, since they will both be derived from the PLL output.

 

Rather, fuse for the 8 MHz calibrated internal RC oscillator.  This oscillator (or a /2 tap of it) is always used as the reference oscillator for the PLL.

 

As I said, you can set that all up in software, and then (also in software, perhaps from a serial console [i.e. you'll need a bit-banged or USI-based serial implementation], or with preprogrammed delays, etc.) tickle OSCCAL to change the frequency of the internal RC oscillator.  That should more-or-less instantly change the internal oscillator used both as the system clock (visible on CKOUT) and as the reference oscillator for the PLL.  Your DSO should see this, and the associated PLL response on OC1A.

 

I expect the PLL will exhibit some latency and possibly some ringing for a short time after a change to OSCCAL.  You could also monitor the PLOCK bit in PLLCSR.  This will tell you when the PLL thinks it is locked.  You could compare that to your own assessment of the PLL's performance.  Perhaps you could just mirror PLOCK on a GPIO in a tight loop and sample it on a third DSO channel.

 

Whatever you're able to come up with, you should resign yourself to the certain knowledge that there is no way to examine (externally or programatically) the phase comparator or the filter.  That is a 'black box' as far as you're concerned.

 

Some things to consider:

 

 

 

 

 

 

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

Last Edited: Sat. Jan 10, 2015 - 07:38 AM
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ka7ehk wrote:

The ONLY relationship between the PLL and the PWM output is the size (duration) of one PWM time slot.

Hey Jim, Thx for reply.


Thx for description of pulse width-- I'm familiar with pulse width, from making electronic music.

I'm not asking if there's a relationship between PWM and PLL in a general sense. Only asking about a causal relationship in the '85 in particular.

Thx again.

Last Edited: Sat. Jan 10, 2015 - 07:25 AM
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Dear sir,

              Thanks for your response. Right now i explain My problem:

I want to fix the register values of LMX 2531 (PLL chip with  integrated VCO) by using the programming of attiny 85 microcontroller. In the data sheet of LMX 2531 it is given that register values can be controlled by using  SPI interface with microcontroller( Latch, Data, clock and chip select signal using SPI).I Tried also c code for this.

#include <tiny85.h>

#include <delay.h>                            
#define data PORTB.0   
#define sck PORTB.4
#define le PORTB.3

void PLL(unsigned int x)

 int i;
 if (x==1)
        {

       //R0 (N= 145, Num= 0)

        int a[24]={1,0,0,1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
        le=0; delay_us(50);
       for(i=0;i<=23;i++)//MSB FIRST 
           { 
                data=a[i]; 
                 
                delay_us(50);
                sck=1;
                delay_us(125);
                sck=0;
                delay_us(50);
           }               
             delay_us(50);
             le=1;

void main(void)
{
// Declare your local variables here
       int j;

// Crystal Oscillator division factor: 1
#pragma optsize-
CLKPR=0x80;
CLKPR=0x00;
#ifdef _OPTIMIZE_SIZE_
#pragma optsize+
#endif

// Input/Output Ports initialization
// Port B initialization
// Func5=Out Func4=Out Func3=Out Func2=Out Func1=Out Func0=Out 
// State5=0 State4=0 State3=0 State2=0 State1=0 State0=0 
PORTB=0x00;
DDRB=0x3F;

// Timer/Counter 0 initialization
// Clock source: System Clock
// Clock value: Timer 0 Stopped
// Mode: Normal top=FFh
// OC0A output: Disconnected
// OC0B output: Disconnected
TCCR0A=0x00;
TCCR0B=0x00;
TCNT0=0x00;
OCR0A=0x00;
OCR0B=0x00;

// Timer/Counter 1 initialization
// Clock source: System Clock
// Clock value: Timer 1 Stopped
// Mode: Normal top=FFh
// OC1A output: Disconnected
// OC1B output: Disconnected
// Timer 1 Overflow Interrupt: Off
// Compare A Match Interrupt: Off
// Compare B Match Interrupt: Off
PLLCSR=0x00;
TCCR1=0x00;
GTCCR=0x00;
TCNT1=0x00;
OCR1A=0x00;
OCR1B=0x00;
OCR1C=0x00;

// External Interrupt(s) initialization
// INT0: Off
// Interrupt on any change on pins PCINT0-5: Off
GIMSK=0x00;
MCUCR=0x00;

// Timer(s)/Counter(s) Interrupt(s) initialization
TIMSK=0x00;

// Universal Serial Interface initialization
// Mode: Disabled
// Clock source: Register & Counter=no clk.
// USI Counter Overflow Interrupt: Off
USICR=0x00;

// Analog Comparator initialization
// Analog Comparator: Off
ACSR=0x80;
ADCSRB=0x00;

     
for(j=0;j<10;j++)
     { 
        
       PLL(7);delay_us(100);
       PLL(8);delay_us(100);
       PLL(6);delay_us(100);
       delay_us(1000);
       PLL(13);delay_us(100);
       PLL(12);delay_us(100);
       PLL(11);delay_us(100);
       PLL(10);delay_us(100);
       PLL(9);delay_us(100);
       PLL(5);delay_us(100);
       PLL(4);delay_us(100);
       PLL(3);delay_us(100);
       PLL(2);delay_us(100);
       PLL(1);delay_us(100);
       le=0;
       } 
     

that is working but i want to know is this correct method to use the attiny 85, port B bit no 4 as clock, bit no 3 as latch enable signal, bit no 0 as data input?

Is there any other method (or by using any other microcontroller) that method shoulg give not deviate in vibration and temperature cycling of aircraft. please suggest and give details of microcontroller

in this project i am giving the 10 MHz  ref frequency (using OCXO of 10 MHz) to ocillator input of LMX 2531 (pin no 31) externally.

Can i give this reffrence oscillator freq to LMX 2531 (at pin 31) using attiny 85. please suggest me?

i am sending you the data sheet of LMX 2531

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lbdubey: You are hijacking this thread! That is NOT a nice thing to do. Just because the original thread had "PLL" in the subject does not make it applicable to your problem.

 

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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Dear sir,

              I am not hijacking any thread. My aim is to sove my problem, not hijacking and all these things if you have answer to amy question then please answer it. My quetion is on PLL +attiny 85 that's why i put there. . My question is this:

I want to fix the register values of LMX 2531 (PLL chip with  integrated VCO) by using the programming of attiny 85 microcontroller. In the data sheet of LMX 2531 it is given that register values can be controlled by using  SPI interface with microcontroller( Latch, Data, clock and chip select signal using SPI).I Tried also c code for this.

#include <tiny85.h>

#include <delay.h>                            
#define data PORTB.0   
#define sck PORTB.4
#define le PORTB.3

void PLL(unsigned int x)

 int i;
 if (x==1)
        {

       //R0 (N= 145, Num= 0)

        int a[24]={1,0,0,1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
        le=0; delay_us(50);
       for(i=0;i<=23;i++)//MSB FIRST 
           { 
                data=a[i]; 
                 
                delay_us(50);
                sck=1;
                delay_us(125);
                sck=0;
                delay_us(50);
           }               
             delay_us(50);
             le=1;

void main(void)
{
// Declare your local variables here
       int j;

// Crystal Oscillator division factor: 1
#pragma optsize-
CLKPR=0x80;
CLKPR=0x00;
#ifdef _OPTIMIZE_SIZE_
#pragma optsize+
#endif

// Input/Output Ports initialization
// Port B initialization
// Func5=Out Func4=Out Func3=Out Func2=Out Func1=Out Func0=Out 
// State5=0 State4=0 State3=0 State2=0 State1=0 State0=0 
PORTB=0x00;
DDRB=0x3F;

// Timer/Counter 0 initialization
// Clock source: System Clock
// Clock value: Timer 0 Stopped
// Mode: Normal top=FFh
// OC0A output: Disconnected
// OC0B output: Disconnected
TCCR0A=0x00;
TCCR0B=0x00;
TCNT0=0x00;
OCR0A=0x00;
OCR0B=0x00;

// Timer/Counter 1 initialization
// Clock source: System Clock
// Clock value: Timer 1 Stopped
// Mode: Normal top=FFh
// OC1A output: Disconnected
// OC1B output: Disconnected
// Timer 1 Overflow Interrupt: Off
// Compare A Match Interrupt: Off
// Compare B Match Interrupt: Off
PLLCSR=0x00;
TCCR1=0x00;
GTCCR=0x00;
TCNT1=0x00;
OCR1A=0x00;
OCR1B=0x00;
OCR1C=0x00;

// External Interrupt(s) initialization
// INT0: Off
// Interrupt on any change on pins PCINT0-5: Off
GIMSK=0x00;
MCUCR=0x00;

// Timer(s)/Counter(s) Interrupt(s) initialization
TIMSK=0x00;

// Universal Serial Interface initialization
// Mode: Disabled
// Clock source: Register & Counter=no clk.
// USI Counter Overflow Interrupt: Off
USICR=0x00;

// Analog Comparator initialization
// Analog Comparator: Off
ACSR=0x80;
ADCSRB=0x00;

     
for(j=0;j<10;j++)
     { 
        
       PLL(7);delay_us(100);
       PLL(8);delay_us(100);
       PLL(6);delay_us(100);
       delay_us(1000);
       PLL(13);delay_us(100);
       PLL(12);delay_us(100);
       PLL(11);delay_us(100);
       PLL(10);delay_us(100);
       PLL(9);delay_us(100);
       PLL(5);delay_us(100);
       PLL(4);delay_us(100);
       PLL(3);delay_us(100);
       PLL(2);delay_us(100);
       PLL(1);delay_us(100);
       le=0;
       } 
     

that is working but i want to know is this correct method to use the attiny 85, port B bit no 4 as clock, bit no 3 as latch enable signal, bit no 0 as data input?

Is there any other method (or by using any other microcontroller) that method shoulg give not deviate in vibration and temperature cycling of aircraft. please suggest and give details of microcontroller

in this project i am giving the 10 MHz  ref frequency (using OCXO of 10 MHz) to ocillator input of LMX 2531 (pin no 31) externally.

Can i give this reffrence oscillator freq to LMX 2531 (at pin 31) using attiny 85. please suggest me?

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Quote:
My quetion is on PLL +attiny 85 that's why i put there.
This thread is about manipulating and inspecting the PLL built into the ATtiny85.

 

You are asking about how to work with the "LMX 2531 (PLL chip with  integrated VCO)" which is a completely separate device.  How is that the same thing?  The fact that you're using an ATtiny85 to do it is not especially relevant.

 

Nobody is upset about it, but adding your question to the end of someone else's completely unrelated thread isn't going to help you to get answers.  Start a new thread with an appropriate title, like "Trouble working with LMX 2531 (PLL chip with  integrated VCO)"

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