Hi there. Can someone please shed some light on the following? I am sure I'm making a stupid arithmetic mistake somewhere:
Clock runs at 4.000 MHz
Timer0 overflows at 8 bit resolution, i.e. 256 times per 4MHz
this interrupt is triggered 15625 times per second.
If I have an ISR that increments a counter every time the overflow occurs, then, in theory, every time this counter reaches 15625 a second has passed, and I increment another counter.
Why is the real-life situation out by at least 20%? (slower)
I can manually by trial and error find the right constant, but this wouldn't work in a mass production environment ;)
Am I missing something in the equation?
If I update my LCD in the ISR, will this prevent the timer from updating properly; i.e. will the counter stop incrementing while it's serving the ISR?
I was considering dedicating the ISR purely to the incrementation and timekeeping, and then updating the LCD from the main's idle loop. Will this help?
Thanks in advance!