Are banked registers saved between mode switches?

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The ARM7 in the SAM7 series has a number of modes with banked CPU registers. Are the banked registers stored between mode switches? For example, when FIQ mode is entered, will R8-R14 contain the same value as the last time FIQ mode was left, or will the banked registers be reset to some known value, eg 0?

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Yes, you have register shadowing in AVR32 architecture. Look in the technical reference manual for the particular core you are interested in (AP7 or UC3).

In general AP7 shadows more registers than UC3, since it is a higher performing architecture.

Hans-Christian

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hce: I think you missed my actual question.

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DidrikM wrote:
hce: I think you missed my actual question.
I tried to my best knowledge to answer what you asked about with regards to the AVR32 architecture. Please feel free to elaborate on what you are asking about.

Hans-Christian

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I know this is an old thread but it ranks first in google right now so I will answer the question:

 

Yes they will contain the values that they were set to before leaving FIQ mode the last time. Banked registers are not reset. Think of them as just another set of registers that are only accessed in a specific mode. Their content will be preserved just like the content of the user-mode registers are preserved when returning from FIQ.

 

This means that you only need to initialize your stack pointer for a particular mode once. And if you dont pop out everything out of the stack when leaving a mode, then your stack will continue to grow when entering that mode again.