XMEGA / Cascading timers using event system

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Hi, I am trying to cascading TCC0 and TCC1 using the event system to generate an interrupt. TCC0 toggles OC0A output and TCC1 counts it. When the count reaches twenty, I want the interrupt to happen. So far no interrupt being generated. I appreciate your suggestions to solve this.

[Codes]

//event system setup using CH0
EVSYS.CH0MUX = EVSYS_CHMUX_TCC0_CCA_gc;

//TCC0 setup: Single Slope PWM toggling OC0A pin
tc_enable(&TCC0);
tc_set_wgm(&TCC0, TC_WG_SS);
tc_write_period(&TCC0, 10);
tc_write_cc(&TCC0, TC_CCA, 7);
tc_enable_cc_channels(&TCC0,TC_CCAEN);
tc_write_clock_source(&TCC0, TC_CLKSEL_DIV1_gc);

//TCC1 setup: Normal mode
tc_set_cca_interrupt_callback(&TCC1,my_callback);
tc_enable(&TCC1);
tc_set_wgm(&TCC1, TC_WG_NORMAL);
tc_write_period(&TCC1, 1000);
tc_write_cc(&TCC1,TC_CCA,20); tc_enable_cc_channels(&TCC1,TC_CCAEN);
tc_write_clock_source(&TCC1, TC_CLKSEL_EVCH0_gc);

-----------------------
xplained a3bu
atmel studio 6.1.2562
asf(3.11.0)
jtagice3

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Are you enabling the interrupts anywhere(?), otherwise no interrupts will be posted at all...

A total newbie to ASF but sei() from the gcc lib is alias'd as

cpu_irq_enable();

-R

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You aren't enabling interrupts. In addition to enabling global interrupts as SH noted, you also need to:

    Enable interrupt level(s) in the PMIC Enable peripheral clock to the Event System (if you are using ASF to configure system clock)
    Set interrupt level(s) on the TC

   // enable all PMIC interrupt levels
   pmic_init();

   // enable interrupts
   cpu_irq_enable();

   // enable peripheral clock to the event system
   sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_EVSYS);

   // set TC overflow interrupt level
   tc_set_overflow_interrupt_level(&TCC1, TC_INT_LVL_LO);

Gamu The Killer Narwhal
Portland, OR, US
_________________
Atmel Studio 6.2
Windows 8.1 Pro
Xplained boards mostly

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Hi All,
Thank you very much for your suggestions. It is working now. However, one more thing I would like to ask you. Is there any way to stop TCC0 immediately after TCC1’s count reaches twenty? That is my goal. Using the interrupt to shut down the timers includes delays, and TCC0 output's count ends up being twenty eight or something like that before its shutdown. I apprecaite your sugestions in advance.

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What is it you are trying to accomplish? I don't see why you need a 32-bit counter when you are counting to 10 with the lower 16 bits and 20 with the upper 16 bits.

Because you are clocking the TC at the same freq as the CPU, the TC will receive many clocks before an ISR can stop the TC clock, as you have experienced. I haven't done anything with the Xmega in a while, but I don't recall a timer mode that stops the counter -- at least not in WGM/OC mode.

Gamu The Killer Narwhal
Portland, OR, US
_________________
Atmel Studio 6.2
Windows 8.1 Pro
Xplained boards mostly

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Hi, Thank you for your feedback, again.
I have a FPGA connected to xmega. The xmega sends strobe pulses out of OC0A to FPGA. FPGA sends data to xmega each time it receives the strobe pulse. The data is stored in the internal SRAM of xmaga using DMA. The number of the strobe pulse will be multiple of 1024 in a real application. The count of twenty above is just for the test purpose. I would like the strobe pulse as fast as possible and so is storing data, while xmega core is handling other tasks. I used the core to create the strobe pulse but not fast enough. That is why I looked into the use of event system and timers for the strobe pulse portion. Thank you.

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I found the solution.
- TCC1 counts the number of pulses out of TCC0 via. event system
- When TCC1's count reaches the target value, DMA writes zero to TCC0's clock selection register to stop TCC0.
The actual number of pulses is more than the target by two pulses but it is far better than using the interrupt.