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 Posted: Mar 17, 2010 - 10:50 PM |
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Joined: Mar 17, 2010
Posts: 2
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I am trying to search about how to do this, but I must be using the wrong terms or something...was hoping someone here could point me in the right direction.
We are going to use an AVR as a slave SPI device to our main micro, and ARM Cortex M-3. Now we would like to support field upgradeability of the AVR through the SPI lines, but all I've read about is actually writing a bootloader on the AVR that talks over SPI and replaces the contents at AVR run-time,
Is there a way we can use the SPI lines to program it just like the hardware programmers (i.e. JTAGICE mkII, or the AVRISP mkII) do...using ISP or PDI? This way we wouldn't have to write a custom bootloader that lives and runs on the AVR, and the ARM Cortex could just fake being a hardware programmer.
Where would I find resources on that? |
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Posted: Mar 17, 2010 - 10:57 PM |
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Joined: Oct 07, 2009
Posts: 55
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| A bootloader is only run ounce every startup if I'm not mistaken, and it doesn't take a lot of of space and is a proven working solution. |
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Posted: Mar 17, 2010 - 11:09 PM |
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Joined: Nov 22, 2002
Posts: 7176
Location: Tangent, OR, USA
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The standard bootloaders use serial port, but any data transport link will work. I would modify an existing loader.
You can, in theory, program it as though your ARM device is a programmer. Check the section "Memory Programming" in your AVR data sheet. It may not be a trivial undertaking but would occupy no additional space in the AVR.
Jim |
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Jim Wagner
Oregon Research Electronics, Consulting Div.
Tangent, OR, USA
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Posted: Mar 17, 2010 - 11:32 PM |
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Joined: Jul 18, 2005
Posts: 33138
Location: (using avr-gcc in) Finchingfield, Essex, England
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| Or download the "Buttload" project and you'll see AVR code that will run on one processor to ISP an AVR. While it's written for AVR mega169 it could be ported to the M3. NXP LPC113X (Cortex M3) call SPI "SSP" in fact. |
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Posted: Mar 17, 2010 - 11:37 PM |
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Joined: May 28, 2006
Posts: 437
Location: Toronto, Canada
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