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 Posted: Dec 06, 2012 - 04:09 PM |
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Joined: Nov 10, 2010
Posts: 8
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Hey,
what is the maximum frequency that could be measured using the input capture module, assume that i'm using Atmega128 on 8MHZ |
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Posted: Dec 06, 2012 - 06:47 PM |
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Joined: Oct 30, 2002
Posts: 5720
Location: The Netherlands
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| Limited by how quickly you can enter the ISR, do work to fetch the value and do something with it, and exit. It's far less then the absolute hardware limit of (I think)) Fcpu/2. |
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Posted: Dec 06, 2012 - 09:44 PM |
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Joined: Jun 22, 2004
Posts: 3849
Location: South West Utah, USA
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The absolute hardware limit is found here. From the data sheet timer/counter section Input Capture Pin Source (page 119):
Both the Input Capture Pin (ICPn) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the Tn pin (Figure 59 on page 143). The edge detector is also identical.
From the data sheet Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers section (page 143):
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fextclk < fclk_io /2) given a 50/50 percent duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_io/2.5.
Fclk_io is the Fcpu clock, which might be divided to a lower frequency (see the XDIV register). Your ICP pin maximum frequency should be less than fclk_io divided by 2.5.
jayjay1947 covered the ISR timing issue (no AVR is capable of processing or even entering any ISR in only 2.5 cycles). Because of this the absolute hardware limits really only apply to the timer/counter external clock input pins or to the analog comparator input pins maximum frequencies.
If you write an assembly code ISR with the smallest possible number of CPU cycles, read the data sheet Interrupt Response Time section, you will find out the maximum ICP capture response speed. Then add how many CPU cycles it takes to display, store or use the ICP result and you have your maximum ICP frequency answer. |
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