| Author |
Message |
|
|
 Posted: Sep 11, 2009 - 07:46 AM |
|
Joined: Apr 01, 2009
Posts: 109
|
|
This is my first breakout board that has a micro-controller and the first to use surface mount components.
I'm not certain how to apply GND pour and/or VCC pour to the top and bottom layers. I've come up with the design based on comments gleaned from these forums. There's too much info via Google, some of which is contradictory. I can't tell the genius' from the fools. 
If you think I need to make additional changes then any comments are welcome. I intend to have this professionally manufactured for my hobbies.
Each port has two 603 components that I may populate with a voltage divider, RC filter, series resistor, or pass-through .... depends on the application.
Rick
Updated Files
Changes
Fixed 2x22pF capacitors to the uC GND (pin 15).
Added a ground plane under the uC footprint (only at the top layer).
Added a ground ring around the crystal.
Moved decoupling capacitors closer to uC.
Added a ground plane at the bottom layer.
Fixed "Acid traps" at bottom left connector.
Fixed missing ground for caps, upper right.
Added 100uF cap. at the pcb's supply point (USB port).
Thank you for helping:
Michael aka icarus1. Very big thank you!!!
DocJC
Heihopp
jesper
Click on picture and open in its own browser window to get a larger image.
Original Files
Click on picture and open in its own browser window to get a larger image.
 |
Last edited by rjburke377 on Sep 12, 2009 - 09:45 PM; edited 4 times in total
|
| |
|
|
|
|
|
|
Posted: Sep 11, 2009 - 08:45 AM |
|
Joined: May 26, 2004
Posts: 1370
Location: Thessaloniki, Hellas
|
|
Nice try and welcome to the SMD area.
There are some things you have to change here:
1. Connect the 2x22pF capacitors ground directly to the uC GND (pin 14).
2. Draw a ground plane under the uC footprint (only at the top layer), and connect it's GND pins there (like you do).
3. Draw a ring ground plane at the crystal.
4. uC decoupling capacitors must be as close as possible to it.
5. Draw a ground plane at the bottom layer to fill your pcb.
6. Don't connect sensitive devices GND and Vsupply pins, to high or unknown ground paths (tracks) - You did it for the uC GND and Vcc. You better put an 100uF cap. at the pcb's supply point and then to draw different ground paths for each different sucircuit. One of them is the micro, another is the USB e.t.c.
5. If your pcb is small enough or/and there are no big currents at the different subcircuits you may follow suggestion 5, else suggestion 6 is better.
I hope this helps. |
_________________
Michael.
User of:
IAR Embedded Workbench C/C++ Compiler
Altium Designer
|
| |
|
|
|
|
|
|
Posted: Sep 11, 2009 - 08:55 AM |
|
Joined: Dec 12, 2004
Posts: 21
Location: Germany
|
|
Hi,
looking at the colors, I guess we are talking about eagle. But it is similar in other programms. You select 'polygon', choose the right layer and draw a rectangle. All other optional selections you find next to the 'width' pull down menu. The polygon rectangle should be bigger than the dimension limiting rectangle on the dimension layer. Now all you have to do is select 'name' and give the new polygon the right signal name 'GND' or whatever you used.
All areas that are not covered can be connected with vias. To update the pcb graphic use 'ratsnest'. Thats it!
Stephen |
|
|
| |
|
|
|
|
|
|
Posted: Sep 11, 2009 - 12:24 PM |
|
Joined: Dec 11, 2007
Posts: 6848
Location: Cleveland, OH
|
|
Doesn't ARef just get a cap to Gnd? You show it tied to V+.
JC |
|
|
| |
|
|
|
|
|
|
Posted: Sep 11, 2009 - 03:42 PM |
|
Joined: Apr 01, 2009
Posts: 109
|
|
|
DocJC wrote:
Doesn't ARef just get a cap to Gnd? You show it tied to V+.
JC
Yup. Bass akwards.
Rick |
|
|
| |
|
|
|
|
|
|
Posted: Sep 11, 2009 - 04:10 PM |
|
Joined: Apr 01, 2009
Posts: 109
|
|
|
icarus1 wrote:
Nice try and welcome to the SMD area. There are some things you have to change here ...
This is exactly what I needed. Thank you. It will take me a while to work through all of your suggestions.
For your first point, the two caps *are* tied directly to pin 15 ground. Are you saying they need to be equal length or and/or their only ground path must be through pin 15?
Rick |
|
|
| |
|
|
|
|
|
|
Posted: Sep 11, 2009 - 04:53 PM |
|
Joined: May 26, 2004
Posts: 1370
Location: Thessaloniki, Hellas
|
|
Rick,
Please open this link:
http://www.necel.com/nesdis/image/U18172EJ2V0UD00.pdf
It is just a datasheet from a NEC microcontroller. Just take a look at Chapter 5.4 (System Clock Oscillators) and you'll understand what I mean. Those thinks are "musts" you have to respect in all of your designs.
I hope this helps. |
_________________
Michael.
User of:
IAR Embedded Workbench C/C++ Compiler
Altium Designer
|
| |
|
|
|
|
|
|
Posted: Sep 11, 2009 - 05:24 PM |
|
Joined: Dec 11, 2007
Posts: 6848
Location: Cleveland, OH
|
|
I think Michael is making some good recommendations, but I am glad he has not seen some of my boards...
You may also wish to add a Version Number and Date to your board. You may, at some time, end up with a Version 2 board, and it will be nice to quickly identify them.
I would try to put a large #1 by pin 1 on the board. Helps keep me from making mistakes at 2:00 AM, when I'm tire, up against a deadline, in a hurry, ...
If you could fit a small pot on the board you could easily connect an LCD, as the pot will be useful for a contrast control. If yo envision it always being on a breadboard, or PCB, then this doesn't matter too much.
JC |
|
|
| |
|
|
|
|
|
|
Posted: Sep 11, 2009 - 05:30 PM |
|
Joined: May 26, 2004
Posts: 1370
Location: Thessaloniki, Hellas
|
|
JC,
Quote:
but I am glad he has not seen some of my boards
Why don't you post an example? |
_________________
Michael.
User of:
IAR Embedded Workbench C/C++ Compiler
Altium Designer
|
| |
|
|
|
|
|
|
Posted: Sep 11, 2009 - 05:44 PM |
|
Joined: Dec 11, 2007
Posts: 6848
Location: Cleveland, OH
|
|
Because:
1) I don't want to steal Rick's thread.
2) I violate more "rules" than I follow.
3) You wouldn't know where to begin with your review.
4) You would not know whether to laugh or cry when you saw some of the stuff I've produced.
5) All of the above. 
JC |
|
|
| |
|
|
|
|
|
|
Posted: Sep 11, 2009 - 05:56 PM |
|
Joined: Apr 01, 2009
Posts: 109
|
|
Michael, that does help. I thought I was going to have to read Japanese for a second! The link doesn't work for me but the document number is good.
Rick |
|
|
| |
|
|
|
|
|
|
Posted: Sep 11, 2009 - 06:22 PM |
|
Joined: May 26, 2004
Posts: 1370
Location: Thessaloniki, Hellas
|
|
No JC,
Don't kill yourself. I believe that there are too few engineers that really know how to make a pcb design. You know this is another science itself. The suggestions that I gave to Rick are really what I learned as experienced in the labs, forums and conversations with other engineers at the same or higher knowledge levels.
Nobody laughs or cry with a good work that sells and fill your coats. An engineer that I know just lit leds (in parallel - without any control of the current), in simple layer pcbs. Now, he has millions of euros and I am trying to learn how to make a host controller to store data in a memory stick. I think that this is really fanny.
Anyway, keep on mooving..... |
_________________
Michael.
User of:
IAR Embedded Workbench C/C++ Compiler
Altium Designer
|
| |
|
|
|
|
|
|
Posted: Sep 11, 2009 - 06:24 PM |
|
Joined: May 26, 2004
Posts: 1370
Location: Thessaloniki, Hellas
|
|
| Rick you don't have to know Japanese. Chapter 5.4 of this micro has 60% pictures than words. Electonics schematics are the same for both Japanese and you. Ha ha ha ... |
_________________
Michael.
User of:
IAR Embedded Workbench C/C++ Compiler
Altium Designer
|
| |
|
|
|
|
|
|
Posted: Sep 11, 2009 - 08:28 PM |
|
Joined: Jun 04, 2007
Posts: 490
Location: Norway
|
|
Nice design 
"Acid traps" at bottom left connector. Edit like bottom right connector.
Acid traps are narrow angles or small gaps that might be a problem when etching the board. |
|
|
| |
|
|
|
|
|
|
Posted: Sep 12, 2009 - 01:04 AM |
|
Joined: Dec 15, 2005
Posts: 958
Location: Brazil
|
|
|
Quote:
Nobody laughs or cry with a good work that sells and fill your coats. An engineer that I know just lit leds (in parallel - without any control of the current), in simple layer pcbs. Now, he has millions of euros and I am trying to learn how to make a host controller to store data in a memory stick. I think that this is really fanny.
Michael seens that this engineer could see a great market for something simple, but the hole thing that he did wasn´t simple, a product that the market absorved... Niceee....
Regards,
Brunomusw |
|
|
| |
|
|
|
|
|
|
Posted: Sep 12, 2009 - 02:20 PM |
|
Joined: Mar 07, 2001
Posts: 2376
Location: Stockholm, Sweden
|
|
| missing ground for caps, upper right. |
_________________
/Jesper
http://www.yampp.com
The quick black AVR jumped over the lazy PIC.
What boots up, must come down.
|
| |
|
|
|
|
|
|
Posted: Sep 12, 2009 - 11:14 PM |
|
Joined: Aug 27, 2007
Posts: 143
Location: Budapest, Hungary
|
|
|
icarus1 wrote:
2. Draw a ground plane under the uC footprint (only at the top layer), and connect it's GND pins there (like you do).
Why is it useful to do so? ( I understand the use of filling the ground plane on the bottom, but this seems to me a bit unnecessary ) |
|
|
| |
|
|
|
|
|
|
Posted: Sep 13, 2009 - 03:55 PM |
|
Joined: Dec 15, 2005
Posts: 958
Location: Brazil
|
|
|
Quote:
Why is it useful to do so? ( I understand the use of filling the ground plane on the bottom, but this seems to me a bit unnecessary )
The return path for the uC should have low impedance, doing a ground plane under the uC helps on it, because the connection with the return path is near to the GND pins.
Regards,
Brunomusw |
_________________
Regards,
Brunomusw
|
| |
|
|
|
|
|
FAQ
Search
Register
Log in to check your private messages
Log in
Maximize
RSS
