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Plons
PostPosted: Aug 29, 2009 - 05:17 PM
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About the title: I needed to shorten the original to Electronics Interfacing 101, a.k.a. Tips & Tricks

About this Sticky Thread:

Certain questions keep coming back, for years and years. And although many fellow freaks are willing to help, it is a bit of a waste to tell the same things over and over again.

Therefor: A sticky thread that will hold a collection of tips and tricks.
It all started here:http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&p=611541#611541

In order to keep this Sticky well-organized, I will moderate this thread extensively: one subject per post. Don't ask questions here, but start a normal thread, and refer (if necessary) to a single subject or post in this thread. See attached snapshot how to get that specific URL.
If you wish to contribute you can post in this thread and refer (if necessary) to the single subject or post as explained above. The moderators of this forum will do the cut and paste actions.

This first post will be used to hold general information on this Sticky, and hold a list of available subjects.

* Interfacing between devices with different logic levels
* About PSU (PowerSupplyUnit) design
* About crystals
etc.

Many thanks to all contributors Exclamation

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Last edited by Plons on Mar 17, 2012 - 05:06 PM; edited 3 times in total
 
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Plons
PostPosted: Aug 29, 2009 - 05:22 PM
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Interfacing between devices with different logic levels

[ka7ehk] Recently, there was a discussion in the General Electronics forum about interfacing between an SDI-12 bus (required 5V logic) and a processor, typically running at 3.3V. The discussion was here, for anyone interested:
http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&t=83056
Glitch finally came up with a solution, and I thought it would be useful to frame it more generally because this is a constant issue that comes up.

First, you should know about the 74AHCTxxx family. It is designed to run from 5V. But, the minimum input logic high level is 2.0V. This means that you can drive it from any logic, including AVR processors, with a supply voltage above about 2.2V, or so. The output will be full-swing 5V. This family is available from TI and several other sources. This appears to also be true for 74HCTxxx (or any of the 74-series logic that ends with "T" in the middle group of letters). What is important about this logic family is that it gives you a way to "step up" an output from a lower logic voltage to 5V

Secondly, you should know about the 74LVCxxx family. It is designed to work from a supply voltage in the range of 1.65V to 5.5V. When powered from the same supply as your processor, its inputs and outputs are directly compatible with the processor. What is really important, however, is that the inputs tolerate +5V input even if the chip is powered by a lower voltage, say 3.3V. This gives you a way of accepting 5V input signals and stepping them down to 3.3V or less.

As a general "philosophical" comment, I would like to point out that many of the logic functions of these two families are available in small-gatecount packages. Different manufacturers call them "1 Gate" or "TinyLogic" or some variation on these names. Most of them are available in SOT-23 packages which are relatively easy to hand-solder due to the wider pin spacing. Many of the basic functions are available for about $0.40US from DigiKey in single quantity. Many will ask why a single gate when you can get 6 or 8 or more in a single package with traditional packages. However, when you do circuit board layout, if logic is needed in widely scattered parts of the circuit, it can be a major challenge just to route the traces to the central chip. Then, it can be a real help to put the logic precisely where it is used.

Many thanks to Glitch who spent some time helping to sort this out.

[leon_heller] MOSFETs are useful for conversion, especially if there are only one or two signals.

[ka7ehk] Agree. You need, however, to watch in low power applications for an MOSFET output that has to idle in the low state. That means it is drawing power though its pull-up resistor. In this case, complementary inverter can save power.

[glitch] I'll just clarify a bit... The 'T' stands for TTL compatible (inputs). Thus the 'AHCT, and 'HCT parts offer CMOS outputs, with TTL compatible inputs. Which is where that 2V threshold comes from.

[DocJC] Illustrations of using the 74HCT series, as well as some examples of High Side Drivers and Load Side Drivers, and simple LED and switch interfaces, which have also come up recently, can be found in a ZBasic Application Note by Don K., AN-213 External Device Interfacing http://www.zbasic.net/appNotes/AN213.pdf
This builds further on what Jim very nicely describes above.
The ZBasic series is based upon AVRs.

[alwech]TI has just released a guide on level translation and has lots of usefull help. http://focus.ti.com/paramsearch/docs/parametricsearch.tsp?familyId=705&family=analog&uiTemplateId=NODE_STRY_PGE_T&CMP=KNC-GoogleTI&247SEM

[dl8dtl] Just for completeness (and though I know Maxim's got a reputation of
suffering from long lead times): Maxim has a number of level shifters
that can translate between a wide range of supply voltages, about 1.2
... 1.8 V minimum on the low-side, and 2.5 ... 5.5 V on the high side.
They are available in various combinations of high-to-low
vs. low-to-high channels. There are also bidirectional translators.
The low-side voltage can be anything between the respective minimum
and the Vcc of the high-side (so you can translate between 1.8 V and
3.3 V, 1.8 V and 5.0 V, or 1.8 V and 2.5 V, for example).

It's the MAX3372...3379 and MAX3390...3393 series. They are, for
example, also used in the JTAG ICE mkII.

[fmaimon] This thread: http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&t=63957&start=0&postdays=0&postorder=asc&highlight=
In this thread, this post from AndersAnd has a very good info about mosfet level translators:
http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&p=569068#569068
and a link to this AN from NXP:
http://www.standardics.nxp.com/support/documents/i2c/pdf/an97055.pdf

[crwper] It's probably overkill, but is there any reason not to use an honest-to-goodness bidirectional level translator like the ADG3304?
http://www.analog.com/static/imported-files/Data_Sheets/ADG3304.pdf
I figure this hasn't been suggested yet for two reasons: (1) cost; and (2) the OP has no need for bidirectional translation.

I'm using this part for a project which requires 1.8V to 3.3V bidirectional translation (I2C), and was surprised to see no mention of its ilk here. Just wanted to make sure I'm not completely out to lunch, as it's my first time using a level translator IC.

Discrete solution: http://www.avrfreaks.net/index.php?name ... 427#445427

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Last edited by Plons on Jul 02, 2012 - 04:16 PM; edited 2 times in total
 
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Plons
PostPosted: Jan 26, 2010 - 11:34 AM
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Joined: Nov 01, 2005
Posts: 6597
Location: Hilversum - the Netherlands

Power supply


A guide for the design of a PSU (power Supply Unit):
http://www.siongboon.com/projects/2005-08-07_lm2576_dc-dc_converter/The%20Power%20Supply.pdf
(Thanks to Bingo600)

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Plons
PostPosted: Mar 17, 2012 - 05:04 PM
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About crystals

A tidy appnote on quartz bitsa.
Hope it is enjoyed.

Ignoramus

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Plons
PostPosted: Mar 22, 2012 - 02:18 PM
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Original post by ka7ehk in the general AVR 8bit Forum.
An oldie but a goody Wink (and yes, of course I mean the info, not the man)

Using 74HC165 on SPI

When you need an extra batch of parallel inputs for an AVR, it is often suggested that you use a shift register, such as 74HC165, on the SPI port. I'm working on a large design that uses several of these, and I would like to share my experiences. If you are not experienced in designing with conventional logic, there are a number of things that could trip you up, here.

1. CHIP SELECT - its not obvious which input to use for the chip select. The input to use is the "CLOCK INHIBIT". When this input is high, changes on the clock line have no effect in the shift register. This is consistent with the normal SPI select sense of "active low".

2. SCK - it connects to the clock input. This should be pretty obvious. Shifts occur on rising clock edges. You have no choice! Thus, your SPI port should be set up to sample on the falling edge, right in the middle of each data bit. This is the Clock Phase bit.

3. SHIFT DIRECTION: Data is shifted out most significant bit (Qh) first. It isn't clear whether or not the Data Order bit (DORD) effects how the master receives data. The spec sheet only describes the effect of this bit on transmitting data. But, I would set DORD to the state that transmits the MSB first.

4. PARALLEL LOAD: The parallel data HAS to be latched into the shift register before it can be shifted out. The /PL line has to go low, then return high, to do this. The clock is locked out while /PL is low. I differentiate the select input to get this logic signal. I use a 47K from /PL input to Vcc. Then, I add a 100pf coupling cap. This makes a pulse width of about 12us. The processor will have to wait about 12us between the time when the select line is asserted and the first rising clock edge. Then, I add a 1K in series with the cap before connecting to the select line. This limits current on the rising edge of the chip select. If you have an unused chip select line, you can use that for /PL instead of the RC network. Just turn on this chip select line for a few instruction cycles before you select the shift register for shifting.

5. DATA OUT: You need to be aware that the data output of the 74HC165 is not SPI compliant. It remains active, not tristate, when it is disabled. If this is the only device in the SPI network, then you don't care. But, if SPI is shared with several devices, you HAVE to tristate it. I use a single gate 74xx125 (available from Fairchild or On Semi or TI). The enable input is active low, so you can connect it directly to the shift register's select line.

6. CASCADING: If you need more than 8 input bit, you can cascade several shift registers. They all use the same clock and select line. Just connect the Qh output of one to the Serial Input of the next. They can all share the same /PL signal and only one tristate buffer is needed. You will need to handle one 8-bit byte for every shift register, while maintaining the select line low the whole time.

7. MISO and MOSI: These shift registers are "read only". Thus, there does not need to be any connection to the Master's MOSI pin. The data output, whether tristated or not, connects to the Master's MISO.

Hope this helps someone out there.

Jim

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jokkebk
PostPosted: Apr 06, 2012 - 08:28 PM
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I'd like to contribute a bit to the first category, voltage shifting. I just finished a detailed write-up on level shifting (both high->low and low->high) with the specific parts 4050B, HCF40109B, 4104B and 74HCT125 covered:

http://codeandlife.com/2012/04/06/level-shifting-101/

For each of the components, I also included measurements with oscilloscope which help to see how the propagation delay in different components affects the maximum usable translation frequency. I hope my investigation helps someone to understand the subject better!

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Plons
PostPosted: Sep 24, 2013 - 09:58 PM
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BSS138 = $0.22 in single quantity, $0.03 in 2000 from DigiKey (not the least expensive). SOT23 so not big. Add one 0603 resistor an you are done. Works really nice inverting or noninverting for low power level translation.

< Posted by JIm in another thread: http://www.avrfreaks.net/index.php?name ... 72#1101572 >

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bobgardner
PostPosted: Sep 25, 2013 - 03:00 PM
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Adafruit ships a cmos 4050 quad buffer with their little 3.3V Nokia 84x48 lcd. Used as a 5V to 3.3V converter. Lets you use the clk and mosi from a 5V uno to talk to it.

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