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 Posted: Jun 30, 2009 - 03:04 PM |
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Joined: Jan 03, 2007
Posts: 44
Location: Graz / Austria
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Hi,
I have to implement access to a 32bit SPI device.
The atmel_spi driver is only supporting 8 and 16bit devices.
I have to use the bit-banging SPI driver therefore 
Does anybody have experience with this bit-banging driver?
How do I have to change board setup?
How do access the driver from userspace?
Thanks,
Gerhard |
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Posted: Jun 30, 2009 - 03:50 PM |
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Joined: Mar 10, 2008
Posts: 68
Location: Zaragoza Spain
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Hi guy,
Upgrade your kernel to 2.6.29. In this version, spi-gpio driver has been added. It uses common gpio framework, which is harware independent.
Take a look at thread (mine  ) " Example code to initialize new spi-gpio driver", dated 2nd of June.
I left default word-width (not sure, 8 bits). It is much slower than atmel_spi. I set clock to 500KHz and worked really well for writing to SPI flash in NGW100.
BR
Ricardo |
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Posted: Jul 01, 2009 - 09:51 AM |
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Joined: Jan 03, 2007
Posts: 44
Location: Graz / Austria
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Hi Ricardo,
thanks for you hint! 
500kHz bit frequency is OK for my application ...
Gerhard |
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Posted: Jul 10, 2009 - 11:58 AM |
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Joined: Aug 19, 2008
Posts: 98
Location: Stockholm, Sweden
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Why doesent atmel fix a decent spi driver that can be accessed from user-space ?
or have they allready ?
I am confused how this can be a problem, why force customers into bit-banging instead of providing a decent driver ?
Or have I missunderstood all this.
I also need to drive a small lcd-display over spi.
/Nicholas |
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Posted: Jul 10, 2009 - 01:39 PM |
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Joined: Jul 27, 2001
Posts: 7429
Location: St. Leonards-on-Sea (UK)
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Just send two or three lots of 8-bit data, there shouldn't be any need for bit-banging. It usually works.
Leon |
_________________
Leon Heller
G1HSM
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Posted: Jul 10, 2009 - 07:20 PM |
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Joined: Jan 03, 2007
Posts: 44
Location: Graz / Austria
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the problem is, that some devices don't like it, if the SPI-CS line goes high (inactive) between multi-byte/multi-word transfers.
I have to read 32bit words from an ADC.
The atmel-spi driver definitely puts SPI-CS high during two 16bit transfers.
Since SPI-CS is controlled via GPIO in the atmel-spi driver, it shouldn't be that big problem to implement 32bit transfers ...
Gerhard |
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Posted: Jul 10, 2009 - 08:23 PM |
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Joined: May 20, 2008
Posts: 13
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I think nobody will prevent you from adapting the atmel-spi-driver. find the line of code and add your adaption for 32-bit-words.
This should be easier than changing to the bit-banging-driver and it is more efficient.
greetings |
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Posted: Jul 13, 2009 - 09:17 AM |
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Joined: Mar 10, 2008
Posts: 68
Location: Zaragoza Spain
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But RDR & TDR registers are 16 bits-wide...
Receiving 32 bits into RDR continously might be problematic? Who knows? I don't.
Ric |
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