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 Posted: Apr 28, 2010 - 02:07 PM |
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Joined: Jan 04, 2010
Posts: 41
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I've got a little circuit setup to serial program an ATtiny2313 using an ATmega164. It's working as it should be, but when I looked at the output on a scope I see large rise times. This led me to discover that I may have been using pull-up resistors with too high a value (200k). I'm just wondering what the maximum input capacitance is for an input pin.
A large portion of my rise times come from the 15pF capacitance of the 10M probes, so I'm not worrying too much about that. I'd just like to know what kind of value I can design around (assuming probes will not be present in the final design).
Thanks,
Trevor |
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Posted: Apr 28, 2010 - 02:11 PM |
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Joined: Jul 27, 2001
Posts: 7429
Location: St. Leonards-on-Sea (UK)
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| 200k is on the high side for a pull-up. 10k is more usual. |
_________________
Leon Heller
G1HSM
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Posted: Apr 28, 2010 - 02:19 PM |
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Joined: Jan 04, 2010
Posts: 41
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| Yeah thanks, I switched over the 200k's to 10k my rise time is definitely limited by the probes now. |
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Posted: Apr 28, 2010 - 06:00 PM |
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Joined: Nov 22, 2002
Posts: 12031
Location: Tangent, OR, USA
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The figure used by Tektronix for CMOS (CD4xxx and 74Cxxx) in DIP package pins has been 7pf. It may now be a bit smaller due to the greatly reduced gate areas on CMOS devices; much of that, however, is physical pin-pin capacitance.
I would guess that it will be smaller, maybe by a factor of 1/2 to 1/3 for SMT packages.
You still have to add in trace capacitance. This will vary with opposite side ground plane, board thickness, trace width and length, and adjacent same-side traces (and the spacing to those traces).
10-20pf (total, including pin capacitance) would not be an unrealistic estimate for common traces up to a few inches long.
Jim |
_________________
Jim Wagner
Oregon Research Electronics, Consulting Div.
Tangent, OR, USA
"The only thing standing between us and victory is defeat" P.G.Wodhouse in Wooster & Jeeves series
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