Forum Menu




 


Log in Problems?
New User? Sign Up!
AVR Freaks Forum Index

Post new topic   Reply to topic
View previous topic Printable version Log in to check your private messages View next topic
Author Message
fabiodl
PostPosted: Jun 27, 2013 - 05:54 AM
Newbie


Joined: Jun 27, 2013
Posts: 5


Hi all,
I read the datasheet,and checked

http://www.avrfreaks.net/index.php?name ... a1+timer+b

but I cannot understand why on an attiny85

Code:
int main(){
    TCCR1|=_BV(CS10);
    GTCCR|=_BV(PWM1B);
    GTCCR|=_BV(COM1B1)|_BV(COM1B0);   
    DDRB|=_BV(PB4); 
    OCR1B=0x80;
    while(1){}
  }


does not work until I add
Code:

    TCCR1|=_BV(COM1A0);


which I guess I should not need if I want to use only timer 1B
 
 View user's profile Send private message  
Reply with quote Back to top
theusch
PostPosted: Jun 27, 2013 - 03:14 PM
10k+ Postman


Joined: Feb 19, 2001
Posts: 28196
Location: Wisconsin USA

IIRC this has come up before, but I can't find the thread. Perhaps this one?
http://www.avrfreaks.net/index.php?name ... errata+pwm
or this?
http://www.avrfreaks.net/index.php?name ... errata+pwm



In any case, there was an errata on very similar behaviour on some revisions of Tiny45. No mention on the '85, but check the errata list to see if it matches your symptoms.
 
 View user's profile Send private message  
Reply with quote Back to top
snigelen
PostPosted: Jun 27, 2013 - 03:34 PM
Posting Freak


Joined: Jan 08, 2009
Posts: 1673
Location: Lund, Sweden

Maybe this thread, with a test program for that bug.
 
 View user's profile Send private message  
Reply with quote Back to top
joeymorin
PostPosted: Jun 27, 2013 - 04:24 PM
Raving lunatic


Joined: Jul 17, 2012
Posts: 2276
Location: Location, Location

theusch wrote:
In any case, there was an errata on very similar behaviour on some revisions of Tiny45. No mention on the '85, but check the errata list to see if it matches your symptoms.
It's possible. The errata mentioned in the datasheet bears at least a resemblance to the OP's problem. However it is not listed among the errata for the ATtiny85, even in the latest revision of the datasheet. I also can't find anything about this in the errata sticky.

Your code does have some problems I think:
Code:
    GTCCR|=_BV(PWM1B);
This mode uses OCR1C as TOP, but you haven't changed it from it's power-on default value of 0x00. TCNT1 will never change from 0x00, but it will cause a compare match to occur on every timer tick.

This:
Code:
    GTCCR|=_BV(COM1B1)|_BV(COM1B0);   
... correctly sets inverting mode for OC1B, but with:
Code:
    OCR1B=0x80;
... a compare match will occur when TCNT1 reaches 0x80, but since OCR1C = 0x00 that will never happen.

Strictly speaking, since you set a prescaler of 1 with:
Code:
    TCCR1|=_BV(CS10);
... before configuring GTCCR, TCNT1 will have counted a couple of ticks by the time you set PWM1B, so TCNT1 will have missed it's first match with the default OCR1B and will count all the way to 0xFF, but only once. On it's way, there will be a compare match with OCR1B and OC1B will be set, but thereafter TCNT1 will be locked at 0x00, and OC1B will be cleared and stay cleared.

snigelen wrote:
Maybe this thread, with a test program for that bug.
If this elicits the 'short flash' behaviour, then the OP has found a new errata.

This statement:
Quote:
does not work until I add
Code:
    TCCR1|=_BV(COM1A0);
... does not reflect the known errata, and even the known errata does not apply to the '85, but it is strange.

Perhaps you can describe exactly what you see. Put a scope on OC1B. What do you see after each instruction in your program? Use _delay_ms(5000) between each line to give you time to see the effect of each:
Code:
#define F_CPU <your_cpu_clock_speed_here>
#include <util/delay.h>

int main() {
  _delay_ms(5000);
   TCCR1|=_BV(CS10);
  _delay_ms(5000);
   GTCCR|=_BV(PWM1B);
  _delay_ms(5000);
   GTCCR|=_BV(COM1B1)|_BV(COM1B0);
  _delay_ms(5000);
   DDRB|=_BV(PB4);
  _delay_ms(5000);
  TCCR1|=_BV(COM1A0);
  _delay_ms(5000);
   OCR1B=0x80;
   while(1){}
}
After examining OC1B, try again examining OC1A for the sake of completeness.

Don't forget to correctly define F_CPU before the #include <util/delay.h>

JJ
 
 View user's profile Send private message  
Reply with quote Back to top
theusch
PostPosted: Jun 27, 2013 - 04:36 PM
10k+ Postman


Joined: Feb 19, 2001
Posts: 28196
Location: Wisconsin USA

Quote:

it is not listed among the errata for the ATtiny85,

Follow sniggie's link above--he found it on some '85s.

Quote:

This mode uses OCR1C as TOP, but you haven't changed it from it's power-on default value of 0x00.

That timer is a "strange beast" for us AVR8 users. As I read the datasheet, there is a 0x00 mode an an OC1C mode, kind of. But you could well be right. I've got simple PWMs for this family in a couple apps but I don't think I've ever fully explored these corners.
 
 View user's profile Send private message  
Reply with quote Back to top
joeymorin
PostPosted: Jun 27, 2013 - 05:17 PM
Raving lunatic


Joined: Jul 17, 2012
Posts: 2276
Location: Location, Location

theusch wrote:
Quote:
it is not listed among the errata for the ATtiny85,
Follow sniggie's link above--he found it on some '85s.
So he has. I just imagined that even the first released '85 post-dates the erratum altogether, and that the latest datasheet from atmel would acknowlege the discovery of this erratum in the '85. Perhaps I'm giving them too much credit Wink

In any case, unless the OP has left something out, what he's describing doesn't quite match this particular erratum. Perhaps it's something new?
Quote:
Quote:
This mode uses OCR1C as TOP, but you haven't changed it from it's power-on default value of 0x00.
That timer is a "strange beast" for us AVR8 users. As I read the datasheet, there is a 0x00 mode an an OC1C mode, kind of. But you could well be right. I've got simple PWMs for this family in a couple apps but I don't think I've ever fully explored these corners.
In fairness, neither have I. I was just going by the datasheet:
Quote:
• Bit 6 – PWM1B: Pulse Width Modulator B Enable
    When set (one) this bit enables PWM mode based on comparator OCR1B in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.
I did spot an error in my analysis. Since PWM1B is set first, the change to OCR1B won't be latched until TCNT1 does it's once-only overflow back to 0x00 = OCR1C, so OC1B will never be set.

JJ

P.S. Why am I being captcha'd when there are no links in this post? (again Mad)
 
 View user's profile Send private message  
Reply with quote Back to top
theusch
PostPosted: Jun 27, 2013 - 06:00 PM
10k+ Postman


Joined: Feb 19, 2001
Posts: 28196
Location: Wisconsin USA

Quote:

P.S. Why am I being captcha'd when there are no links in this post? (again

Ummm--have you looked in the mirror lately? Twisted Evil "Profiling" at its best...
 
 View user's profile Send private message  
Reply with quote Back to top
joeymorin
PostPosted: Jun 27, 2013 - 06:11 PM
Raving lunatic


Joined: Jul 17, 2012
Posts: 2276
Location: Location, Location

theusch wrote:
Quote:
P.S. Why am I being captcha'd when there are no links in this post? (again
Ummm--have you looked in the mirror lately? Twisted Evil "Profiling" at its best...
That's rich, coming from the poster child for BSE Wink

Actually, I have somewhat more hair than my avatar suggests...
 
 View user's profile Send private message  
Reply with quote Back to top
Torby
PostPosted: Jun 27, 2013 - 10:06 PM
Raving lunatic


Joined: Nov 11, 2003
Posts: 5783
Location: Broken Arrow OK USA

Quote:
Actually, I have somewhat more hair than my avatar suggests...


Not for long!

_________________
Torby

You can't always believe everything you think.
 
 View user's profile Send private message Visit poster's website 
Reply with quote Back to top
joeymorin
PostPosted: Jun 27, 2013 - 10:36 PM
Raving lunatic


Joined: Jul 17, 2012
Posts: 2276
Location: Location, Location

Torby wrote:
Quote:
Actually, I have somewhat more hair than my avatar suggests...
Not for long!
The bow tie is meant to distract...
 
 View user's profile Send private message  
Reply with quote Back to top
fabiodl
PostPosted: Jun 29, 2013 - 09:11 AM
Newbie


Joined: Jun 27, 2013
Posts: 5


Thank you to all you guys.
I changed the code to
Code:
OCR1C=0xFF;
  GTCCR|=_BV(PWM1B);
  TCCR1|=_BV(COM1A0);
  GTCCR|=_BV(COM1B1)|_BV(COM1B0);   
  TCCR1|=_BV(CS10);
  DDRB|=_BV(PB4)|_BV(PB3)|_BV(PB0)|_BV(PB1); 
  OCR1A=0x1;
  OCR1B=0x40;

and I can confirm that the config
_BV(COM1A1)|_BV(COM1A0)==0
GTCCR|=_BV(COM1B1)|_BV(COM1B0);
is the only configuration that does not work as expected.
I checked whether the problem is the same of the attiny45, i.e. that the two configs should be the same, but that is not the case.
b.t.w, it is an attiny85v, it says 101S attiny85v 10PU


Last edited by fabiodl on Jun 30, 2013 - 09:30 AM; edited 1 time in total
 
 View user's profile Send private message  
Reply with quote Back to top
joeymorin
PostPosted: Jun 29, 2013 - 01:28 PM
Raving lunatic


Joined: Jul 17, 2012
Posts: 2276
Location: Location, Location

Do you still find that:
Code:
  TCCR1|=_BV(COM1A0);
... is necessary for getting OC1B/PB4 to show a PWM signal?
Quote:
and I can confirm that the config
_BV(COM1B1)|_BV(COM1B0)==0
GTCCR|=_BV(COM1B1)|_BV(COM1B0);
is the only configuration that does not work as expected.
???
Do you mean not setting _BV(COM1B1) and _BV(COM1B0) in GTCCR? That config disconnects OC0B from PB4, so this is normal.

JJ
 
 View user's profile Send private message  
Reply with quote Back to top
theusch
PostPosted: Jun 29, 2013 - 01:32 PM
10k+ Postman


Joined: Feb 19, 2001
Posts: 28196
Location: Wisconsin USA

Quote:

I checked whether the problem is the same of the attiny45, i.e. that the two configs should be the same, but that is not the case.

That may well depend on the silicon version of the '45. And perhaps the '85s as well.
 
 View user's profile Send private message  
Reply with quote Back to top
fabiodl
PostPosted: Jun 30, 2013 - 09:31 AM
Newbie


Joined: Jun 27, 2013
Posts: 5


joeymorin wrote:

Do you mean not setting _BV(COM1B1) and _BV(COM1B0) in GTCCR? That config disconnects OC0B from PB4, so this is normal.

JJ


sorry, I corrected my post, I meant _BV(COM1A1) and _BV(COM1A0)
 
 View user's profile Send private message  
Reply with quote Back to top
joeymorin
PostPosted: Jul 01, 2013 - 04:16 AM
Raving lunatic


Joined: Jul 17, 2012
Posts: 2276
Location: Location, Location

fabiodl wrote:
sorry, I corrected my post, I meant _BV(COM1A1) and _BV(COM1A0)
That seems to describe a situation different from the known erratum.

Can anyone confirm this behaviour in another ATtiny85?

JJ
 
 View user's profile Send private message  
Reply with quote Back to top
snigelen
PostPosted: Jul 01, 2013 - 07:29 AM
Posting Freak


Joined: Jan 08, 2009
Posts: 1673
Location: Lund, Sweden

IIRC, there was identical behaviour when I tested on a '45 and a '85 and that the workaround suggested in the errata was only one way to get it to work.
 
 View user's profile Send private message  
Reply with quote Back to top
Display posts from previous:     
Jump to:  
All times are GMT + 1 Hour
Post new topic   Reply to topic
View previous topic Printable version Log in to check your private messages View next topic
Powered by PNphpBB2 © 2003-2006 The PNphpBB Group
Credits