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thinki_cao
PostPosted: Jul 11, 2012 - 03:22 PM
Newbie


Joined: Jul 08, 2012
Posts: 10
Location: Nanjing,China

Hi,

I just started to use AS6, and I'm porting the ucos-II on ATmega128 recently.

I take the OS_CRITICAL_METHOD=3. When I enter the critical segment, I store the SREG register in the local variable cpu_sr and execute cli. When I exit the critical segment ,I restore the SREG register from the cpu_sr. The corresponding code is:

Code:
void  OSTimeDly (INT16U ticks)
{
#if OS_CRITICAL_METHOD == 3     /* Allocate storage for CPU status register */
    OS_CPU_SR  cpu_sr;
#endif   


    if (ticks > 0) {                                                   
        OS_ENTER_CRITICAL();
        if ((OSRdyTbl[OSTCBCur->OSTCBY] &= ~OSTCBCur->OSTCBBitX) == 0) {
            OSRdyGrp &= ~OSTCBCur->OSTCBBitY;
        }
        OSTCBCur->OSTCBDly=ticks;                                       
        OS_EXIT_CRITICAL();
        OS_Sched();                                                       
    }
}


The MACRO is:

Code:
#if      OS_CRITICAL_METHOD == 3
#define      OS_ENTER_CRITICAL()      cpu_sr=SREG;   \
                                      cli()
#define      OS_EXIT_CRITICAL()      SREG=cpu_sr
#endif

Here is the problem, I use the AS6 Simulator to debug and I found the code above can't store or restore the SREG register and I can't tell whether it is the Simulator's bug or the code's bug.
I upload several pictures to describe this phenomenon.

picture1
http://img2.ph.126.net/N_mdx1OwHShf3qAWjvI9OA==/2604206484544728802.jpg
Before execute the OS_ENTER_CRITICAL(), note that I bit in SREG is SET.

picture2
http://img9.ph.126.net/9SmF4QKzhjTaqon-YKWCNQ==/2655997880259490329.jpg
After execute the OS_ENTER_CRITICAL(), note that SREG is stored in the R20 and I bit in SREG is cleared.

picture3
http://img2.ph.126.net/N_mdx1OwHShf3qAWjvI9OA==/2604206484544728802.jpg
After execute the OS_EXIT_CRITICAL(), note that though "out 0x3f,R20" has been executed but SREG is not as same as the previous one before OS_ENTER_CRITICAL() execution. The most essential thing is that the I bit is still ZERO!

ps:I've checked that the R20 register has been unchanged and is always 0x80 during the whole process above!


I use the latest version of AS6 build 1843 and GCC-AVR 3.4.0.65.

Here is the project
 
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clawson
PostPosted: Jul 11, 2012 - 03:54 PM
10k+ Postman


Joined: Jul 18, 2005
Posts: 62944
Location: (using avr-gcc in) Finchingfield, Essex, England

Quote:

and I found the code above can't store or restore the SREG register and I can't tell whether it is the Simulator's bug or the code's bug.

See previous thread about this - there's no question, this is a bug in the AS6 simulator so no need to worry. The simulated CPU *does* behave as if I is set when it is even if you cannot see this.

EDIT: found the thread...

http://www.avrfreaks.net/index.php?name ... highlight=

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meolsen
PostPosted: Jul 11, 2012 - 04:02 PM
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Joined: Jul 27, 2011
Posts: 582
Location: Atmel, Norway

This is also resolved internally, see external bug at http://asf.atmel.no/bugzilla/show_bug.cgi?id=2275

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thinki_cao
PostPosted: Jul 12, 2012 - 04:25 AM
Newbie


Joined: Jul 08, 2012
Posts: 10
Location: Nanjing,China

clawson wrote:
Quote:

and I found the code above can't store or restore the SREG register and I can't tell whether it is the Simulator's bug or the code's bug.

See previous thread about this - there's no question, this is a bug in the AS6 simulator so no need to worry. The simulated CPU *does* behave as if I is set when it is even if you cannot see this.

EDIT: found the thread...

http://www.avrfreaks.net/index.php?name ... highlight=


Thanks!I got it! Very Happy
 
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thinki_cao
PostPosted: Jul 12, 2012 - 04:27 AM
Newbie


Joined: Jul 08, 2012
Posts: 10
Location: Nanjing,China

meolsen wrote:
This is also resolved internally, see external bug at http://asf.atmel.no/bugzilla/show_bug.cgi?id=2275


I found the solution form the link Very Happy

Quote:
The SREG register is correctly altered if the simulation is run, but fails when
single stepping.
 
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