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 Posted: Apr 16, 2012 - 03:33 PM |
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Joined: Sep 01, 2008
Posts: 40
Location: Melbourne, Australia
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I recently obtained some '128s marked "ATMEGA128 8AU 0947" and began using them in one of our standard products. We previously used type ATMEGA128 8AC but they are currently unobtainable. The device uses an 8MHz crystal and we set the AtoD ADCSRA divider to 0x6, or divide by 64, giving an AtoD clock of 125 KHz and inside the 50-200 KHz boundary.
However, now with this setting the AtoD readings are always full scale.
Changing the divider to /128 fixes the problem but presumably the clock is now running at 62.5 KHz, near the lower boundary.
Anyone else seen this effect? |
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Posted: Apr 16, 2012 - 09:33 PM |
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Joined: Feb 09, 2012
Posts: 223
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This should not happen with any avr microcontroller.
Both chip have a voltage range of 2.7V to 5.5V, but the "8AU" has a larger temperature range. I think that also the DC-characteristics differ.
Is your circuit beyond the specs? Is there something like voltage, decoupling capacitors, impedance of analog signal,... that is not within the specifications? |
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Posted: Apr 16, 2012 - 10:47 PM |
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Joined: Feb 19, 2001
Posts: 25904
Location: Wisconsin USA
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If I had to guess, it would be an "override" of ADMUX selecting a different reference.
Post the smallest complete program that demonstrates the symptoms.
Quote:
We previously used type ATMEGA128 8AC but they are currently unobtainable.
You may never find them again. The '128A is out now. The "temperature grades" and "speed grades" are pretty much eliminated except for "extended" types such as automotive. |
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Posted: Apr 17, 2012 - 01:55 AM |
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Joined: Sep 01, 2008
Posts: 40
Location: Melbourne, Australia
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Here is a short program (avrStudio 5.1) that shows the defect. Use just ADPS2 and ADPS1 giving 125 KHz and all readings are full scale, regardless of input. Include ADPS0 giving 62.5 KHz and it works. Using a spare pin (PA7) and a 'scope gives a 210uS pulse which fits with the nominal 208 uS spec, so it really is a 62.5 Khz ADC clock. So the question is: why does a 125 KHz clock not work?
Only thing a little unusual is a VCC of 4.2V (battery) and an AREF of precision 1.0V.
Code:
#include <avr/io.h>
static void SettleTime(void);
uint16_t Reading;
//-------------------------------------------------------------------
// Crystal is 8 MHz.
//
int main(void)
{
uint8_t val;
// ADCSRA = (1<<ADEN) | (1<<ADPS2) | (1<<ADPS1); // 64
ADCSRA = (1<<ADEN) | (1<<ADPS2) | (1<<ADPS1) | (1<<ADPS0); // 128
ADMUX = 0;
DDRA |= 0x80;
while(1)
{
SettleTime();
PORTA |= 0x80; // scope trigger
ADCSRA |= (1<<ADSC); // start the next conversion
while (ADCSRA & (1<<ADSC)) {;} // wait until ready
PORTA &= ~0x80; // scope trigger
val = ADCL; // low byte
Reading = (uint16_t)val;
val = ADCH; // high byte
Reading += (uint16_t)val << 8;
}
}
Cheers
Ron |
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Posted: Apr 17, 2012 - 02:16 AM |
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Joined: Mar 28, 2001
Posts: 20358
Location: Sydney, Australia (Gum trees, Koalas and Kangaroos, No Edelweiss)
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| Why not just
Code:
Reading = ADCW;
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_________________
John Samperi
Ampertronics Pty. Ltd.
www.ampertronics.com.au
* Electronic Design * Custom Products * Contract Assembly
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Posted: Apr 17, 2012 - 07:50 AM |
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Joined: Feb 09, 2012
Posts: 223
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How long is the delay in SettleTime().
Is your AREF 1.0 V ? Is that below the specs ? |
Last edited by Kun.io on Apr 17, 2012 - 05:59 PM; edited 1 time in total
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Posted: Apr 17, 2012 - 02:15 PM |
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Joined: Feb 19, 2001
Posts: 25904
Location: Wisconsin USA
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Quote:
V VREF Reference Voltage 2.0 AVCC
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Posted: Apr 18, 2012 - 06:32 AM |
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Joined: Sep 01, 2008
Posts: 40
Location: Melbourne, Australia
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Yes, why not ADSW! Change made.
It looks like the 2V VREF spec is the problem, although stability and calibration are ok at 62.5 KHz.
Cheers All. |
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