AVRFreaks.net

Mannin,

[...]
In this processor is it possible to set-up the A12-A15 address pins as GPIOs? If so, do that, then write a simple loop to walk-thru the 16 state possiblilities which scoping or DVMing in a static, or near-static, condition. [...]

When using adresses from 0xB000 to 0xFFFF I see the proper signals on the inputs of the 74HC138.

However I got a permanent High signal on every output.

How are you measuring those?

One would normally deduce, that it is not enabled correctly on G1/G2A/G2B!

I got one of these fantastic XProtolabs from Gabotronics which means I can only measure roughly at this frequency

but I see peaks on the correct Pins.

G1 is tied to A15 and shows of course the same peak as the other Adress lines -> is that a problem?

You need some gating signal that tells when an address is valid.
It depends on what you plan to connect to the outputs of the 138.

[...]
Edit: if you use ALE as "address is valid"-signal, and connect it to G2A or G2B, you will have clean and glich-free outputs.

But are the peaks valid logic signals?

The output of the 138 controls the CS for an 8255A. A0-A1 are used as inputs to the 8255A on this extension card whereas A12-A15 are used to chose between different cards(different CS).

8255 were not too fast at the gest of times.

Then my suggestion for using ALE on G2A or G2B will do fine. Rd and Wr on the 8255A will take care of the rest.

Do I really need to do this?

Yes. The address-lines A8~A15 change level when ALE is high. Decoding without ALE to G2A or G2B will result in spikes on the outputs during level-change of A8~A15.

About the 74HCT138N (I assume you mean 74HCT138N): I checked the datasheet, and I see no reason for the need of a 2 NOP delay.
Can you post the complete schematic and the test SW ?

Edit: 2 NOP delay ?? Are you writing to the IO-ports instead of using the external memory interface ? And how do you set SRWn1 and SRWn0 ??

Yes I tested everything by writing to the IO-ports because it worked with static levels

Yes I'm sending out data using the UART(and delays in between).

The 16MHz shouldn't be a problem for the 138 either right?

Which should confirm that CKDIV is programmed ? What is the baudrate and what value is in the baudrate register ?

Now you got me puzzled. I/O clock is what counts. And that should be 2MHz (as you mentioned earlier) because that is what you need for external memory timing. The 8255A's need appr. 300ns for read and write.

At 16MHz, the period is 62.5ns. With direct I/O port access as in the published SW, incl the 2 NOP's, the fastest way of writing gives 3 times the 62.5ns = 187.5ns.

I suggest you stick with assembler when sorting out things like this. Or at least have a look at the resulting assemblercode.

All the IO-Port tests are done with the 8255A disconnected. To evaluate the problem with the 138 step by step.

However I'm still having issues interfacing the 8255A.

When you write "137", do you mean the 74HCT138 ?
When you write "537", do you mean the 74HCT573, the octal latch ?

ALE is used to latch the lower address bits before portA is used as databus.

Have a look at your schematic: you are using ALE (PE2) also as bootloader switch input. With 10nF on that pin it will be tough for PE2 to generate ALE

And once again: did you connect ALE to G2A (last time I ask) ?

Okay. Next step.

The odd looking signal looks like a line that is tri-stated (floating) It was high during the /Cs

[...]
Put the channel with the trigger of the scope on the 8255A-/CS-pin, negative edge triggered. Channel 2 on 8255A-/Rd and Channel 3 on 8255A-/Wr. What is the width of the /Rd and /Wr pulse ?
And are the /Rd and /Wr pulse low during /Cs ?
/Cs must go low first; when true /Rd or /Wr can go low but all that time /Cs must be stable and low. So /Cs comes first, leaves last.
<dinner>

The 8255A uses the High Active Reset.

When I use a delay of 2secs at the very beginning of the program

I can write to the 8255 but can't read anymore. I hope the scope will shed some light on this.

Edit: Do I need a special SRW0 and SRW1 setting? Currently I'm using the default values(0)

T1 does take care of that, if ST1-B22 is going to the 8255A's Reset.

That should be enough

Yeah that's why I put him there

Do I need a special SRW0 and SRW1 setting? Currently I'm using the default values(0)

You're right, the name ST1-B22 gave it away

But you do have indeed an issue with the Reset for the 8255A.
When the AVR is still in reset-mode, the 8255A is already out of it (when voltage on NRES rises above 0.8V, the Reset for the 8255A goes low). And since the AVR-pins are configured as inputs, that may cause all kins of oddities.
To fix that: you could tweak the circuit around T1, but better is to use an I/O-pin for that. Old technology mix with today's technology requires that. Use a pull-up of 4k7 and make the pin low when YOU (in SW) think it's time for the 8255A to come out of reset-mode.

No, with 2MHz I/O-clock you're fine. But if you need more speed for the AVR and use f.i. a 4MHz max 5MHz crystal (CKDIV8 Fuse not set), SRWn1 = 0 and SRWn0 = 1 is needed to meet the 8255A timing requirements.
Nard

What kind of tweak did you have in mind?

Sacrificing an IO is next to impossible since I'm already lacking about 10 I/Os

Okay. Next step.

The odd looking signal looks like a line that is tri-stated (floating) It was high during the /Cs

Before looking at the data, you need to make sure that the timing for the 8255A is correct.
To check that: write a small program that writes data to the 8255A, then reads data from it; then make it pause for 100us or so. And loop.
Put the channel with the trigger of the scope on the 8255A-/CS-pin, negative edge triggered. Channel 2 on 8255A-/Rd and Channel 3 on 8255A-/Wr. What is the width of the /Rd and /Wr pulse ?
And are the /Rd and /Wr pulse low during /Cs ?
/Cs must go low first; when true /Rd or /Wr can go low but all that time /Cs must be stable and low. So /Cs comes first, leaves last.

2. Do yemember that I asked for the wirelength between 1287 and the 8255's ? Do you see the oscillations on the edges of all signals ?

That may be (or become) a problem. It's due to the high slewrate nowadays technology is capable of, where the 1980 PPI 8255A wasn't aware of that speed.

But before that: when the systems are up and running, short the base of T1 to ground and release. Now make the 1287 do it's 8255 init and try a write and read once more. Still a bad read ?

Edit: what is your defenition for an unsuccessfull read ?

One really strange thing:

When switching read and write resulting in:

Read
delay(100us)
Write
delay(1s)

it works(read and write)

I need to ask: are you familiar and comfortable with the 8255's ?

Do you have pull-ups on the Port I/O side ?

If the extra reset with shorting the base of T1 doesn't have effect, we must do something on the oscillations. Not knowing how your system setup looks like, I need to make an educated guess: add 330 Ohm resistors to /Cs, /Rd and /Wr. Put these resistors close to their source (so not at 8255-side) Check with your (nice) scope. Use 10x Probes and short groundleads.

There are no pull ups between the 8255A and the AVR.

I could only add those by extending all lines between AVR and 8255 by 20cm.

I could only add those by extending all lines between AVR and 8255 by 20cm.

That looks much better.

Since the PPI's are Nmos, their busdriving-high capability is poor. Add 8 pull-ups to the databus, 3k3 ~ 4k7 should be fine. And this time I mean the databus between PPI and AVR.

PS there is no write-action in the pictures.

Okay. Next step.
The odd looking signal looks like a line that is tri-stated (floating) It was high during the /Cs

Do you have any idea what could cause this?

Then on WP_000058.jpg : could one of those jumpers be loose ? Connector row A pin 7
That would explain the different behaviour of the AD7 signal, compared with AD0.

It was the soldering I was resoldering the wrong pins all the time.... However one of the boards I was testing with was broken.... And without the 330Ohm in the /WR, /RD and CS line it still doesn't work... have to take that into consideration when redesigning the board.

Thanks alot for all this help Nard. One more question. It works without the suggested pullups on the data lines should I design them in anyway?

Bad solder-joints aside: the oscillation on the /WR, /RD, and the 5 /CS's needs to be eliminated. My 330 Ohm was a best guesstimate, but you need to look at these signals also when the AVR-board is in the 19" rack: to see if the 330 Ohm is sufficient.

What is your plan on the shortage of I/O ? Do yourself a big favour and control the Reset for the PPI's with an I/O from the 1287. Then YOU are in control, not an unpredictable RC-network with schmitt-trigger.

I would favor a solution with a small helping AVR(Or maybe a UC3 like the ones on the Xplains handling the USB aswell?) However since this is supposed to be a learning system I have to find a solution which is very easy to understand and use.