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 Posted: Sep 15, 2011 - 06:33 PM |
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Joined: Jun 18, 2011
Posts: 8
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Hi,
the AppNote AVR1300 under Conversion Speed says:
Quote:
For
XMEGA A devices the ADC clock should not be set higher than 2 MHz, for XMEGA D
devices the top frequency limit is 1.4 Mhz. Lowest ADC clock frequency for both
XMEGA A and XMEGA D devices are 100 kHz. See device datasheet for more
information.
There is no Minimal ADC Clock frequency value in the ATXMEGA128A1 datasheet.
(under ADC Characteristics --> ADC Clock frequency)
But I can find it in the newer ATxmega128A4U datasheet.
So the minimal ADC Clock frequency is 100 KHz and not what in various links is suggested to use (like 62KHz).
When using the internal 32MHz oscillator with prescaler 256 it is 125KHz because prescaler 512 would be below specs, right ?
Thanks
MAK3 |
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Posted: Sep 16, 2011 - 02:41 AM |
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Joined: Apr 25, 2005
Posts: 139
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I would go with recommendations from Atmel in this case- not something offered up on a web site. There are likely engineering reasons the minimum speed is specified, although I too don't understand why the minimum ADC clock speed is only mentioned in AN1300.
Any particular reason you would want to slow it down to less than 100KHz? |
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Posted: Sep 16, 2011 - 11:47 AM |
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Joined: Jun 18, 2011
Posts: 8
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Quote:
Any particular reason you would want to slow it down to less than 100KHz?
Because of the high impedance of source I want to measure.
I wanted to avoid an external circuit like impedance converter.And according the AVR1300 datasheet (Figure 3-9) say for source impedance > 1,0E+5 the sample rate should be below 100KHz which is then out of spec.
MAK3 |
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Posted: Sep 26, 2011 - 04:14 PM |
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Joined: Sep 22, 2011
Posts: 91
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If there was really a minimum speed for the ADC, wouldn't this have been integrated into the corresponding XMEGA "adc.h" ASF code as an assertion or logical rule? The current ASF code in function adc_set_clock_rate() only verifies that the requested rate is not zero, and that it is less than or equal to the maximum (2 MHz for "A" XMEGA or 1.4 MHz for "D" XMEGA).
In fact, it seems to work without issue to use the maximum pre-scaler even at CPU/peripheral clock rates below 32 MHz. You can clock the CPU at 2 MHz and use the 512 scaler to get an ADC sampling rate of 3906 Hz and all seems to proceed as expected, i.e. you get conversions completed at the speed you'd expect and the data is good. Or at least, this all seems fine when I do this on the XMEGA-A1 Xplained when sampling the data coming from the light sensor... |
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