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 Posted: Sep 10, 2012 - 07:58 PM |
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Joined: Oct 26, 2011
Posts: 29
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Hey folks,
I'm just tinkering around with some old hardware. I have some old PROM chips from the Commodore 64 (info available here http://symlink.dk/nostalgia/c64/rom/ ). I got the idea that it would be a fun project to try to read them just for the practice and fun of it.
So I'm going to use a couple of shift registers for the address lines, and I will wire up the digital output directly to the avr.
I have a few questions:
1. Does anyone know if I need to worry about voltage on these old chips? I think 5v should be fine but I don't want to fry anything!
2. In terms of sending out the address I want to read, I know that A0-A4 are column and A5-A12 are row, but I'm not sure how to determine what addresses I should send to each. Do I just start at 0x00 and increment?
3. /CS do I hold CS high or low? Or does the chip do that to tell me when to read?
Thanks guys
Mark |
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Posted: Sep 10, 2012 - 08:05 PM |
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Joined: Nov 17, 2004
Posts: 13961
Location: Vancouver, BC
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2) Starting from 0 and incrementing should be correct, but the C64 may have done something strange with the hook-up of the address lines.
3) Hold it low. |
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Regards,
Steve A.
The Board helps those that help themselves.
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Posted: Sep 10, 2012 - 09:08 PM |
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Joined: Oct 30, 2002
Posts: 5727
Location: The Netherlands
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Row and column addressing is something from the DRAM world, not simple parallel ROMs 
From the description on the symlink.dk site I don't think Commodore did anything strange with the address lines, just plain sequential hookup; e.g. A0..A11 are really connected to A0..A11 of the CPU.
I would not bother with shiftregisters. It's just 21 lines so you need an AVR with 21 spare GPIOs. Where does the read data end up? Sent to a PC via a serial link? |
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Posted: Sep 10, 2012 - 09:29 PM |
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Joined: Oct 26, 2011
Posts: 29
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jayjay1974 wrote:
Row and column addressing is something from the DRAM world, not simple parallel ROMs
From the description on the symlink.dk site I don't think Commodore did anything strange with the address lines, just plain sequential hookup; e.g. A0..A11 are really connected to A0..A11 of the CPU.
I would not bother with shiftregisters. It's just 21 lines so you need an AVR with 21 spare GPIOs. Where does the read data end up? Sent to a PC via a serial link?
Yeah I was going to send it over via serial.
The datasheet shows Row and Column (http://www.zimmers.net/anonftp/pub/cbm/documents/chipdata/2364.zip) on the last page. "Column Decoder" and "Row Decoder"
Thanks for all the help guys, you're great! |
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Posted: Sep 10, 2012 - 09:48 PM |
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Joined: Jul 18, 2005
Posts: 62944
Location: (using avr-gcc in) Finchingfield, Essex, England
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Quote:
The datasheet shows Row and Column
That's just showing how the device is organised internally. From an external perspective you simply count A12..A0 from 0x0000 to 0x1FFF and you get each byte in turn output on D0..D7. Simple as that. |
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Posted: Sep 10, 2012 - 11:22 PM |
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Joined: Dec 30, 2004
Posts: 9009
Location: Melbourne,Australia
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| A simpler way of creating the address is to use a 74hc4040 counter. You only need two ports bits- reset and clock. |
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Posted: Sep 11, 2012 - 01:00 AM |
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Joined: Sep 04, 2002
Posts: 21396
Location: Orlando Florida
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| Read the 8 bit data byte at each location and look up the 6502 mnemonic and how many bytes of operand address for that opcode and you can just print out the disassembled dump. |
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Imagecraft compiler user
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Posted: Sep 11, 2012 - 01:34 AM |
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Joined: Oct 26, 2011
Posts: 29
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clawson wrote:
Quote:
The datasheet shows Row and Column
That's just showing how the device is organised internally. From an external perspective you simply count A12..A0 from 0x0000 to 0x1FFF and you get each byte in turn output on D0..D7. Simple as that.
Wow. That is just way too simple
Thanks! |
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Posted: Sep 11, 2012 - 10:23 AM |
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Joined: Jul 18, 2005
Posts: 62944
Location: (using avr-gcc in) Finchingfield, Essex, England
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Quote:
That is just way too simple
1970's..1980's computer technology WAS that simple
In fact ROMs were often used as state machine/pattern generators. Without a micro you could have the D0.D7 behave differently according to the input A0..An. For example you could simply have a counter that ran through the addresses and the 8 outputs were effectively completely programmable at each step - no need for a micro in this. |
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Posted: Sep 11, 2012 - 11:02 AM |
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Joined: Jan 03, 2006
Posts: 4447
Location: Hemel Hemsptead, UK
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| My homebrew processor (avrfreaks passim) used eeproms as the arithmetic logic unit; four bits in from each of two operands, plus a carry in, and three (four?) bits to define the operation; four bits plus carry and zero out. Two of those used together gave me the eight bit ALU in two chips instead of a whole eurocard full of 74 logic. It ate current, though, and was nowhere near as quick... |
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Neil Barnes
www.nailed-barnacle.co.uk
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Posted: Sep 11, 2012 - 03:42 PM |
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Joined: Feb 15, 2011
Posts: 76
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I used to repair those things years ago.
I do not know if I have any old chips left over.
However this article is useful for other old tech.
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Posted: Sep 11, 2012 - 04:01 PM |
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Joined: Apr 16, 2001
Posts: 3526
Location: Phoenix, Arizona
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| Or use an AVR with external memory access and talk to the ROM using an 8-bit bus structure with an address latch. I know the Mega8515 will do this, not sure if any newer AVR's still support external memory. |
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Posted: Sep 11, 2012 - 06:36 PM |
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Joined: Dec 06, 2007
Posts: 2512
Location: Redmond, WA USA
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dksmall wrote:
not sure if any newer AVR's still support external memory.
Any of you AVR part gurus feel like filling in the blanks on this? |
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Larry
Those afraid to embrace the future will quickly fade into the past. - larryvc
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Posted: Sep 11, 2012 - 06:46 PM |
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Joined: Oct 30, 2002
Posts: 5727
Location: The Netherlands
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I tried finding out using the parametric table on the Atmel site. It's useless!
But what is the definition of newer? |
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Posted: Sep 11, 2012 - 07:27 PM |
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Joined: Jul 18, 2005
Posts: 62944
Location: (using avr-gcc in) Finchingfield, Essex, England
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The 8515, mega162, nega64, mega128 all have external memory interfaces to my certain knowledge. Not sure of others though a grep of the .h files for the right control registers should weedle them out.
Needless to say that most of the "large pinout" Xmega all have an EBI which I guess is the modern way to do it.
EDIT: A look at a few datasheets seems to suggest the XMEM devices are likely to have SRW01 (to do with wait state select) so...
Code:
E:\WinAVR-20100110\avr\include\avr>grep SRW01 *.h
iocanxx.h:#define SRW01 1
iom128.h:#define SRW01 3
iom161.h:#define SRW01 3
iom162.h:#define SRW01 3
iom32u6.h:#define SRW01 1
iom64.h:#define SRW01 3
iom8515.h:#define SRW01 3
iomxx0_1.h:#define SRW01 1
iousbxx6_7.h:#define SRW01 1
That would seem to confirm I listed most of them above. |
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Posted: Sep 11, 2012 - 07:57 PM |
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Joined: Apr 16, 2001
Posts: 3526
Location: Phoenix, Arizona
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jayjay1974 wrote:
But what is the definition of newer?
Newer then a Mega8515.  |
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Posted: Sep 12, 2012 - 02:51 AM |
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Joined: Oct 27, 2011
Posts: 9
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The 64's 6510 used banked switching, as it had 64k of RAM and just 16 address lines. The ROM was found in the second bank.
For you reference the reset vector for the 64 is $FFFC-$FFFD, that should point you to the start of the 64's Kernal (kernel) at $E000 if you are interested in investigating it.
I would use a 7400 series parallel latch for addressing but remember the prom's would be very slow, even by the standards of todays slowest EEPROM's. Make sure this timing issue is taken into account. |
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Posted: Sep 12, 2012 - 03:25 AM |
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Joined: Dec 06, 2007
Posts: 2512
Location: Redmond, WA USA
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Forgot about a bug I had reported about devices that have external ram, the keyword was XRAM. Thanks to Cliff's example above I came up with this list of devices with XRAM that are listed in the Studio 6.0/devices folder. Seems to be missing a couple of the devices that were indicated in Cliff's list above.
Code:
C:\Program Files (x86)\Atmel\Atmel Studio 6.0\devices>grep XRAM *.xml
AT90CAN128.xml: <memory-segment name="XRAM" start="0x1100" size="0xef00" type="ram" external="1"/>
AT90CAN32.xml: <memory-segment name="XRAM" start="0x0900" size="0xf700" type="ram" external="1"/>
AT90CAN64.xml: <memory-segment name="XRAM" start="0x1100" size="0xef00" type="ram" external="1"/>
AT90USB1286.xml: <memory-segment name="XRAM" start="0x2200" size="0xde00" type="ram" external="1"/>
AT90USB1287.xml: <memory-segment name="XRAM" start="0x2200" size="0xde00" type="ram" external="1"/>
AT90USB646.xml: <memory-segment name="XRAM" start="0x2200" size="0xde00" type="ram" external="1"/>
AT90USB647.xml: <memory-segment name="XRAM" start="0x2200" size="0xde00" type="ram" external="1"/>
ATmega128.xml: <memory-segment name="XRAM" start="0x1100" size="0xef00" type="ram" external="1"/>
ATmega1280.xml: <memory-segment name="XRAM" start="0x2200" size="0xde00" type="ram" external="1"/>
ATmega1281.xml: <memory-segment name="XRAM" start="0x2200" size="0xde00" type="ram" external="1"/>
ATmega128A.xml: <memory-segment name="XRAM" start="0x1100" size="0xef00" type="ram" external="1"/>
ATmega162.xml: <memory-segment name="XRAM" start="0x0500" size="0xfb00" type="ram" external="1"/>
ATmega2560.xml: <memory-segment name="XRAM" start="0x2200" size="0xde00" type="ram" external="1"/>
ATmega2561.xml: <memory-segment name="XRAM" start="0x2200" size="0xde00" type="ram" external="1"/>
ATmega64.xml: <memory-segment name="XRAM" start="0x1100" size="0xef00" type="ram" external="1"/>
ATmega640.xml: <memory-segment name="XRAM" start="0x2200" size="0xde00" type="ram" external="1"/>
ATmega64A.xml: <memory-segment name="XRAM" start="0x1100" size="0xef00" type="ram" external="1"/>
ATmega8515.xml: <memory-segment name="XRAM" start="0x0260" size="0xfda0" type="ram" external="1"/>
Code:
=====================================================================================================
OT: I liked it better when I was in the UTC+1 time zone. |
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Larry
Those afraid to embrace the future will quickly fade into the past. - larryvc
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Posted: Sep 13, 2012 - 12:03 AM |
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Joined: Oct 26, 2011
Posts: 29
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Hi guys,
I did it In case anyone cares, the chip I am dumping contains the 901227-2 kernel - the program just spits out the hex values of each memory location. Maybe I'll write something in Python to save a .bin file for me now
Here's a screen shot of the terminal:
I didn't have an avr with enough pins to spare so I cheated and used a PIC18F4520 that I had on the bench. Fun stuff - thanks for your help! |
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