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 Posted: Jun 12, 2012 - 07:53 PM |
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Joined: Nov 22, 2002
Posts: 12198
Location: Tangent, OR, USA
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This may, at first, seem to be a generic c question, but what I wonder about is the actual implementation.
Suppose that you have an 8-bit hardware register, REG. And, you write:
REG |= 0b00010001;
Does it get implemented in the AVR-universe as a read of of REG into a temporary register, followed by the bitwise-OR, and then a write back? Or, if that register happens to be at an address that allows bit-set operations, does it do 2 bit-sets? Does the choice of bitset or full-byte OR depend on the number of bits that are true in the constant?
What happens if it is ORed with a variable?
Is the operation guaranteed to be atomic in either implementation?
And, what happens with a 16-bit hardware register?
Is this behavior consistent across compilers, especially targeting different processor families?
Thanks again!
Jim |
_________________
Jim Wagner
Oregon Research Electronics, Consulting Div.
Tangent, OR, USA
"The only thing standing between us and victory is defeat" P.G.Wodhouse in Wooster & Jeeves series
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Posted: Jun 12, 2012 - 08:00 PM |
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Joined: Jul 18, 2005
Posts: 62949
Location: (using avr-gcc in) Finchingfield, Essex, England
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Jim,
As you posted in avr-gcc forum you will find that if only ONE bit is being changed and the target is in range of SBI/CBI (so 0x00..0x1F) then yes it uses an atomic SBI/CBI instruction but if more bits are being changed in uses IN/op/OUT - sdly it does not do two SBI/CBI when just 2 bits are being changed.
As soon as an RMW is used it's not atomic so the programmer should be aware of this and protect if necessary.
BTW it's easy to try stuff out to find out - this for mega16:
Code:
PORTB |= 0b00100000;
92: c5 9a sbi 0x18, 5 ; 24
PORTB |= 0b01000100;
94: 88 b3 in r24, 0x18 ; 24
96: 84 64 ori r24, 0x44 ; 68
98: 88 bb out 0x18, r24 ; 24
PORTB |= 0b10010011;
9a: 88 b3 in r24, 0x18 ; 24
9c: 83 69 ori r24, 0x93 ; 147
9e: 88 bb out 0x18, r24 ; 24
TIMSK |= 0b00000001;
a0: 89 b7 in r24, 0x39 ; 57
a2: 81 60 ori r24, 0x01 ; 1
a4: 89 bf out 0x39, r24 ; 57
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Last edited by clawson on Jun 12, 2012 - 08:02 PM; edited 1 time in total
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Posted: Jun 12, 2012 - 08:01 PM |
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Joined: Jan 12, 2002
Posts: 7832
Location: Canada
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| It will most likely do a Read-OR-Write operation as you first described [for multi-bit sets]. However there are no hard and fast rules here, if you want to know what YOUR compiler is doing... you will have to look at the generated code from your compiler for the optimization settings you have selected. [results likely will differ between compilers, versions of compilers and optimization levels] |
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Posted: Jun 12, 2012 - 08:27 PM |
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Joined: Nov 22, 2002
Posts: 12198
Location: Tangent, OR, USA
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Thanks, folks -
At my "normal" computer, Windows (and, hence Studio) comes via VMWare. The computer, not being mine, is severely memory-challenged, and takes a good 5 minutes to get Windows on its feet. Its reasonable, once running, but takes forever to get there. Thus, its not so easy to investigate what should be easy test cases.
Sorry for the noise!
Jim |
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Jim Wagner
Oregon Research Electronics, Consulting Div.
Tangent, OR, USA
"The only thing standing between us and victory is defeat" P.G.Wodhouse in Wooster & Jeeves series
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Posted: Jun 12, 2012 - 08:33 PM |
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Joined: Mar 27, 2002
Posts: 18761
Location: Lund, Sweden
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Quote:
takes a good 5 minutes to get Windows on its feet
Luxury...
(Sorry, couldn't resist!) |
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Posted: Jun 12, 2012 - 08:40 PM |
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Joined: Oct 30, 2002
Posts: 5727
Location: The Netherlands
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Quote:
sdly it does not do two SBI/CBI when just 2 bits are being changed.
Probably because that's not the same as in/or/out where all bits change state simultaneously. |
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Posted: Jun 12, 2012 - 09:22 PM |
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Joined: Jan 08, 2009
Posts: 1202
Location: Lund, Sweden
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JohanEkdahl wrote:
Luxury...
(Sorry, couldn't resist!)
Oh, Monty Python?
Monty Python wrote:
Luxury. We used to have to get out of the lake at six o'clock in the morning, clean the lake, eat a handful of 'ot gravel, work twenty hour day at mill for tuppence a month, come home, and Dad would thrash us to sleep with a broken bottle, if we were lucky!
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Posted: Jun 12, 2012 - 09:25 PM |
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Joined: Feb 19, 2001
Posts: 26115
Location: Wisconsin USA
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Quote:
Or, if that register happens to be at an address that allows bit-set operations, does it do 2 bit-sets?
Let's say the compiler did that. Now, you would have a glitch of a couple AVR cycles. But the programmer wants/needs them to be set at the same time! Shoot-through, anyone?
As is demonstrated above, if you want two bit sets then program two single-bit operations.
Atomicity is indeed a concern. My short answer is it shouldn't be too hard to look at the ISRs and note any I/O work done there--it usually isn't much. If none, then the mainline shouldn't need to worry about atomicity. |
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Posted: Jun 12, 2012 - 09:46 PM |
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Joined: Dec 21, 2006
Posts: 1551
Location: Saar-Lor-Lux
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ka7ehk wrote:
This may, at first, seem to be a generic c question, but what I wonder about is the actual implementation.
Suppose that you have an 8-bit hardware register, REG. And, you write:
REG |= 0b00010001;
Does it get implemented in the AVR-universe as a read of of REG into a temporary register, followed by the bitwise-OR, and then a write back?
Yes.
ka7ehk wrote:
Or, if that register happens to be at an address that allows bit-set operations, does it do 2 bit-sets?
No. That would be a bug with respect to volatile correctness.
"What comprises a volatile access" is implementation defined, yet implementations chose to translate to code that has the same number of reads and the same number of writes in the same order as given by the source code.
ka7ehk wrote:
Does the choice of bitset or full-byte OR depend on the number of bits that are true in the constant?
It depends on the available instructions, of course. If there are no atomic operations that have the same volatile footprint, the you cannot use such operations, of course.
ka7ehk wrote:
What happens if it is ORed with a variable?
Same. IN-OR-OUT or LDS-OR-STS cum granum salis.
ka7ehk wrote:
Is the operation guaranteed to be atomic in either implementation?
No. Not even PORTB |= 1 is guaranteed to be atomic, even if SBI is available. The compiler tries to use it but there is no guarantee. For example, try avr-gcc without optimization.
ka7ehk wrote:
And, what happens with a 16-bit hardware register?
Same. even if just bit 0 is changes to high part must be loaded/stored to satisfy volatile correctness.
ka7ehk wrote:
Is this behavior consistent across compilers, especially targeting different processor families?
That will depend on the compiler and on the target. For gcc see for example
• gcc: What constitutes an access to an object that has volatile-qualified type
There are situations where the compiler inforinges volatile correctness, for example on AVR, some SFRs behave differently with SBI compared to an IN-OR-OUT sequence. Yet the avr-gcc might use SBI in that case.
For an example see this post and the subsequent discussion. |
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Posted: Jun 12, 2012 - 09:52 PM |
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Joined: Nov 22, 2002
Posts: 12198
Location: Tangent, OR, USA
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Thanks -
I really appreciate the explanation. Pretty much makes sense!
I vaguely recall reading somewhere on this list that wrapping the non-atomic operations in sei/cli pair does not really achieve atomic operation. Is this true? If so, is this generally true across compilers?
Thanks
Jim |
_________________
Jim Wagner
Oregon Research Electronics, Consulting Div.
Tangent, OR, USA
"The only thing standing between us and victory is defeat" P.G.Wodhouse in Wooster & Jeeves series
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Posted: Jun 12, 2012 - 10:05 PM |
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Joined: Feb 19, 2001
Posts: 26115
Location: Wisconsin USA
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Quote:
I vaguely recall reading somewhere on this list that wrapping the non-atomic operations in sei/cli pair does not really achieve atomic operation. Is this true? If so, is this generally true across compilers?
Oh, wow--I more than vaguely recall it, but it will take some time perhaps to dig out. IIRC GCC might re-order code in certain cases, and your cli/sei may not end up where you think they might. Digging...
[edit] I think there is another thread similar to this link, but this should give you an idea of sei/cli handling in GCC and the recommendation to use atomic.h:
http://www.avrfreaks.net/index.php?name ... torder=asc
This next link is to a thread that doesn't address the issue quite as directly. However, read it through and follow the links to the prior discussions. Interesting stuff:
http://www.avrfreaks.net/index.php?name ... torder=asc |
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Posted: Jun 12, 2012 - 10:39 PM |
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Joined: Oct 29, 2006
Posts: 2690
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ka7ehk wrote:
REG |= 0b00010001;
Does it get implemented in the AVR-universe as a read of of REG into a temporary register, followed by the bitwise-OR, and then a write back? Or, if that register happens to be at an address that allows bit-set operations, does it do 2 bit-sets? Does the choice of bitset or full-byte OR depend on the number of bits that are true in the constant?
Except in the single-bit case, read-modify-write is the only allowed implementation.
The definition of access is implementation-defined and that provides a lot of wiggle-room, but two consecutive writes could produce an externally visible surprise.
Even an SBI in the single-bit case can produce arguments.
Also SBI, SBI would be slower than IN, ORI, OUT.
Quote:
What happens if it is ORed with a variable?
Read-modify-write.
Quote:
Is the operation guaranteed to be atomic in either implementation?
No.
Quote:
And, what happens with a 16-bit hardware register?
Definitely not atomic.
In fact, assignments to distinct 16-bit registers can interfere with each other.
They can share intermediate high bytes that exist to allow atomicity when assigning 16-bit registers.
Quote:
Is this behavior consistent across compilers, especially targeting different processor families?
Some depend on the available instruction set and therefore must be consistent.
Atomicity cold be provided. |
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Michael Hennebry
Iluvatar is the better part of Valar.
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Posted: Jun 12, 2012 - 11:09 PM |
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Joined: Nov 22, 2002
Posts: 12198
Location: Tangent, OR, USA
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| Duhhh, of course you would not want two non-simultaneous bit-set operations when the code implies simultaneous. As in
Code:
REG |= 0b00010001;
Comes from not thinking things through well enough. But, discussions like this DO help the clear thinking thing.
Thanks, all!
Jim |
_________________
Jim Wagner
Oregon Research Electronics, Consulting Div.
Tangent, OR, USA
"The only thing standing between us and victory is defeat" P.G.Wodhouse in Wooster & Jeeves series
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Posted: Jun 13, 2012 - 05:51 AM |
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Joined: Dec 16, 2005
Posts: 3097
Location: Bratislava, Slovakia
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If you desire control, use asm.
JW |
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Posted: Jun 13, 2012 - 07:51 AM |
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Joined: Dec 21, 2006
Posts: 1551
Location: Saar-Lor-Lux
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Assembler is not that trivial, because in general you don't want to propagate the need of assembly to the whole function. That is: you want to use inline assembler.
How would an inline assembler function C code look like that cared for all situations in the best way?
• SBI available or not?
• IN/OUT available or not?
• Mask is a power of two or not?
• LAS instruction available or not? |
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avr-gcc News • ABI • Options • 4.8-Windows • Inline Asm
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Posted: Jun 13, 2012 - 09:55 AM |
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Joined: Dec 16, 2005
Posts: 3097
Location: Bratislava, Slovakia
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Control means you know what are you doing, and you do it deliberately and willingly. So there's no free lunch, read, pre-chewed automatism, sorry.
JW |
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Posted: Jun 13, 2012 - 10:02 AM |
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Joined: Jul 18, 2005
Posts: 62949
Location: (using avr-gcc in) Finchingfield, Essex, England
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Quote:
I vaguely recall reading somewhere on this list that wrapping the non-atomic operations in sei/cli pair does not really achieve atomic operation. Is this true? If so, is this generally true across compilers?
This was because sei() and cli() are basically just one line asm macros that insert SEI or CLI opcodes and there is no guarantee about the ordering of where they appear. Now maybe this has changed in later iterations of the compiler but this was the reason for Dean Camera adding <util/atomic.h> to AVR-LibC:
http://www.nongnu.org/avr-libc/user-man ... tomic.html
As that article notes someone very near here wrote this:
http://www.nongnu.org/avr-libc/user-man ... de_reorder
Do remember that atomicity is only an issue when dealing with something that is actually shared between main() and ISR() so if you limit those (or pick naturally atomic entities) you can reduce the requirement for atomicity protection. |
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Posted: Jun 13, 2012 - 05:17 PM |
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Joined: Nov 22, 2002
Posts: 12198
Location: Tangent, OR, USA
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Thanks for the clarification on "atomic". As earlier, the insight is genuinely appreciated.
Now, if there were a simple way to "bookmark" such threads to make later access simpler, when the grey matters fail to recover the key details .....
Jim |
_________________
Jim Wagner
Oregon Research Electronics, Consulting Div.
Tangent, OR, USA
"The only thing standing between us and victory is defeat" P.G.Wodhouse in Wooster & Jeeves series
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Posted: Jun 13, 2012 - 06:11 PM |
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Joined: Oct 30, 2002
Posts: 5727
Location: The Netherlands
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| Ctrl-D... at least in FF. |
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Posted: Jun 13, 2012 - 10:15 PM |
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Joined: Mar 27, 2002
Posts: 18761
Location: Lund, Sweden
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I run a password protected wiki on a web hotel, and there I can edit wiki pages making notes of all sorts of stuff. E.g. links to interesting threads here at AVRfreaks.
Thus I can reach them form any Internet-able computer. |
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Posted: Jun 14, 2012 - 09:04 AM |
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Joined: Jul 18, 2005
Posts: 62949
Location: (using avr-gcc in) Finchingfield, Essex, England
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Quote:
Thus I can reach them form any Internet-able computer.
Can't you store your "password vault" as a PGP encrypted document there then?  |
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Posted: Jun 14, 2012 - 09:52 AM |
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Joined: Dec 06, 2007
Posts: 2512
Location: Redmond, WA USA
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clawson wrote:
Can't you store your "password vault" as a PGP encrypted document there then?
How is Johan going to remember/access the password for the web hotel when it is in the "password vault"? |
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Larry
Those afraid to embrace the future will quickly fade into the past. - larryvc
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Posted: Jun 14, 2012 - 01:58 PM |
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Joined: Mar 27, 2002
Posts: 18761
Location: Lund, Sweden
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The two remarks above are referring to another thread, where I was asking for opinions re "password repository applications". My answer to the two comments above can be ound in that thread.
Or rather, it won't. The crappy dorum software on the edge of collapse now refuses to show the listings pages of my posts (only first page works, then it is just crap). Atmel should be embarrased aout the state of this site, but obviously care for more or less about $1 worth.
Just consider this and the two preceding posts OT static and proceed with the RMW discussions. |
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