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 Posted: May 30, 2012 - 06:53 AM |
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Joined: Feb 19, 2010
Posts: 507
Location: Montreal, QC, CA
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Quote:
The AVRs can have code and data in flash, but can only have data in ram.
I think you meant:
AVRs can have data in flash or RAM, but can only have code in flash.
In contrast, the architecture of the ARM processor has a single internal bus for both code and data, as opposed to two separate buses on the AVR. On an ARM code can be either in flash or RAM. |
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Posted: May 30, 2012 - 08:03 AM |
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Joined: Oct 05, 2006
Posts: 2250
Location: Poland
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Perhaps you do not know it yet, but it is a debugger that you actually need.
OT:
hugoboss wrote:
In contrast, the architecture of the ARM processor has a single internal bus for both code and data
AFAIK only CM0 have a single bus. Other ARMs(including mature v5) have separate program/data buses. Some of ARMs uCs have even more of them, for example LPC1769 has four buses.
Perhaps you meant "the architecture of the ARM processor has a single internal memory space"? If so, some tiny AVRs have one memory space and about all the rest of AVRs have FLASH+SRAM(+EEPROM sometimes).
hugoboss wrote:
On an ARM code can be either in flash or RAM.
Indeed, that is a cool feature. One can dll a code from about any SD. |
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Posted: May 31, 2012 - 12:18 AM |
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Joined: Dec 18, 2001
Posts: 4717
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The ARMs are single-address-space for RAM/Flash. This is called Harvard Architecture.
The AVR and PIC are dual-address busses. This is called von Neuman Architecture.
Problem is that C and other compilers, and the standardized run time libraries were designed for the single address space architecture and hacked and kludged for dual address spaces; some better than others (GCC is sub-par in this regard).
ARM is so nice in having RAM and Flash in the single address space. You can run code in either, e.g., debug in RAM, then write to flash. And the ARM chip makers do tricks to keep the cycle time for instruction fetches from flash just as fast as from RAM - e.g., by having a 128 bit wide flash data bus. |
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Posted: May 31, 2012 - 12:47 AM |
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Joined: Sep 04, 2002
Posts: 21274
Location: Orlando Florida
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| Harvard 'architecture'->AVRs; Von Neuman architecture-> ARMs, Pentiums, 6800s, 'conventional' computers. |
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Imagecraft compiler user
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Posted: May 31, 2012 - 06:32 AM |
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Joined: Mar 28, 2001
Posts: 20392
Location: Sydney, Australia (Gum trees, Koalas and Kangaroos, No Edelweiss)
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Quote:
The ARMs are single-address-space for RAM/Flash. This is called Harvard Architecture.
The AVR and PIC are dual-address busses. This is called von Neuman Architecture.
Exactly the OPOSITE as Bob seems to show cryptically.  |
_________________
John Samperi
Ampertronics Pty. Ltd.
www.ampertronics.com.au
* Electronic Design * Custom Products * Contract Assembly
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Posted: May 31, 2012 - 09:50 AM |
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Joined: Oct 05, 2006
Posts: 2250
Location: Poland
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stevech wrote:
The ARMs are single-address-space for RAM/Flash. This is called Harvard Architecture.
http://infocenter.arm.com/help/topic/co ... index.html
Cortex-M0 Generic Users Guide wrote:
The Cortex-M0 processor is built on a high-performance processor core, with a 3-stage pipeline von Neumann architecture
bobgardner wrote:
Von Neuman architecture-> ARMs
http://infocenter.arm.com/help/topic/co ... index.html
Cortex-M3 Generic Users Guide wrote:
The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture
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Posted: May 31, 2012 - 03:20 PM |
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Joined: Dec 06, 2007
Posts: 2512
Location: Redmond, WA USA
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| Add a PIC32 to the mix and you get a hybrid of the two architectures. |
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Larry
Those afraid to embrace the future will quickly fade into the past. - larryvc
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Posted: May 31, 2012 - 05:25 PM |
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Joined: Sep 04, 2002
Posts: 21274
Location: Orlando Florida
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| OK, I give. If the instructions are in ram, they can be modified. I did it in the 6800. |
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Imagecraft compiler user
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Posted: May 31, 2012 - 11:48 PM |
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Joined: Mar 28, 2001
Posts: 20392
Location: Sydney, Australia (Gum trees, Koalas and Kangaroos, No Edelweiss)
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Quote:
If the instructions are in ram, they can be modified. I did it in the 6800.
True but only in a single buss architecture where RAM and FLASH/ROM/EEPROM bear no distinction as to data or code or even, in the case of the 6800 I/O space, the von Neumann architecture.
In a, say M8515, where you can add 64K of RAM, instructions in that space are useless as the CPU will not see anything there as code, the Harvard (or rather MODIFIED Harvard) architecture.
Edit
Quote:
QUESTION
What is the difference between Harvard Architecture and von Neumann Architecture?
ANSWER
The name Harvard Architecture comes from the Harvard Mark I relay-based computer. The most obvious characteristic of the Harvard Architecture is that it has physically separate signals and storage for code and data memory. It is possible to access program memory and data memory simultaneously. Typically, code (or program) memory is read-only and data memory is read-write. Therefore, it is impossible for program contents to be modified by the program itself.
The von Neumann Architecture is named after the mathematician and early computer scientist John von Neumann. von Neumann machines have shared signals and memory for code and data. Thus, the program can be easily modified by itself since it is stored in read-write memory.
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_________________
John Samperi
Ampertronics Pty. Ltd.
www.ampertronics.com.au
* Electronic Design * Custom Products * Contract Assembly
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