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 Posted: Apr 11, 2012 - 05:17 PM |
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Joined: Nov 01, 2005
Posts: 6326
Location: Hilversum - the Netherlands
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With an I/O-clock of 2 MHz, the period is 500ns. If the C-compiler uses the quickest way to set the I/O-register, there is always at least 500ns between the two instructions. And that should be no problem for the 138. No NOP's required.
The fact that you need the 2 NOP's points to an I/O-clock of 16 MHz. Are you positive about the setting of the CKDIV-fuse ? |
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Posted: Apr 11, 2012 - 05:25 PM |
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Joined: Dec 09, 2010
Posts: 154
Location: BW, Germany
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| Yes I'm sending out data using the UART(and delays in between). The 16MHz shouldn't be a problem for the 138 either right? |
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Posted: Apr 11, 2012 - 05:50 PM |
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Joined: Nov 01, 2005
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Location: Hilversum - the Netherlands
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Quote:
Yes I'm sending out data using the UART(and delays in between).
Which should confirm that CKDIV is programmed ? What is the baudrate and what value is in the baudrate register ?
Quote:
The 16MHz shouldn't be a problem for the 138 either right?
Now you got me puzzled. I/O clock is what counts. And that should be 2MHz (as you mentioned earlier) because that is what you need for external memory timing. The 8255A's need appr. 300ns for read and write.
At 16MHz, the period is 62.5ns. With direct I/O port access as in the published SW, incl the 2 NOP's, the fastest way of writing gives 3 times the 62.5ns = 187.5ns.
I suggest you stick with assembler when sorting out things like this. Or at least have a look at the reulting assemblercode. |
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Posted: Apr 11, 2012 - 06:17 PM |
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Joined: Dec 09, 2010
Posts: 154
Location: BW, Germany
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Plons wrote:
Quote:
Yes I'm sending out data using the UART(and delays in between).
Which should confirm that CKDIV is programmed ? What is the baudrate and what value is in the baudrate register ?
Baudrate is 9600 the Registers are set accordingly(I hope so  )
Code:
UCSR1A = 0x00;
UCSR1B = (1 << TXEN1);
UCSR1C = (1 << UCSZ11) | (1 << UCSZ10);
UBRR1 = 12;
But since my main routine with enabled UART is basically doing:
Code:
XMEM_READ/IO-Manipulation
UART transmit
delay of 1000ms
it should be easy to tell the difference between 1s delay(clock as expected) and 1/8s delay(Using 16MHz by mistake)
Quote:
Quote:
The 16MHz shouldn't be a problem for the 138 either right?
Now you got me puzzled. I/O clock is what counts. And that should be 2MHz (as you mentioned earlier) because that is what you need for external memory timing. The 8255A's need appr. 300ns for read and write.
At 16MHz, the period is 62.5ns. With direct I/O port access as in the published SW, incl the 2 NOP's, the fastest way of writing gives 3 times the 62.5ns = 187.5ns.
I suggest you stick with assembler when sorting out things like this. Or at least have a look at the resulting assemblercode.
All the IO-Port tests are done with the 8255A disconnected. To evaluate the problem with the 138 step by step. |
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Posted: Apr 11, 2012 - 06:29 PM |
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Joined: Nov 01, 2005
Posts: 6326
Location: Hilversum - the Netherlands
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Ah, that's nice: UBRR1 = 12 which results in 9600bd @ 2MHz
So we can be sure of the I/O-clock setting to 2 MHz.
Quote:
All the IO-Port tests are done with the 8255A disconnected. To evaluate the problem with the 138 step by step.
OK. Just wanted to make sure we're on the same track.
<dinnertime> |
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Posted: Apr 11, 2012 - 09:59 PM |
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Joined: Nov 01, 2005
Posts: 6326
Location: Hilversum - the Netherlands
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What scope picture do you get on Y3 of the 138 with this asm-loop:
Code:
LDI R25,&HA0
LDI R26,&HB0
Again:
OUT PortC,R26
OUT PortC,R25
NOP
NOP
RJMP Again
Y3 should be low for appr. 500ns and high for 2.5us (if I did the math right)
And becuase of the slow response: are you positive that the 138 is supplied with 5V and that there is a cap of 0.1uF over it's supplypins ? Common grounds ?
These questions may look silly but need to be asked. |
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Posted: Apr 12, 2012 - 06:38 AM |
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Joined: Jan 03, 2006
Posts: 4417
Location: Hemel Hemsptead, UK
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| I was indeed wondering whether the 138 was actually powered, and not just operating on leakage from its input logic signals. I get a lot of this sort of thing at work and it's quite confusing when you turn the power off on a unit and the damn thing keeps right on working... |
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Neil Barnes
www.nailed-barnacle.co.uk
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Posted: Apr 12, 2012 - 02:54 PM |
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Joined: Dec 09, 2010
Posts: 154
Location: BW, Germany
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| It seems that it was only a soldering issue.... after soldering a new 1287 to the board the CSs are generated fine. However I'm still having issues interfacing the 8255A. Writing doesn't work at all and Reading works only for Bit0-Bit5. I'll open another thread for it tonight if I can't figure it out. |
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Posted: Apr 12, 2012 - 03:20 PM |
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Joined: Nov 01, 2005
Posts: 6326
Location: Hilversum - the Netherlands
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I just got it setup 
Code:
$asm
LDI R25,&H30
LDI R26,&HB0
Again:
Out Porta , R25
Out Porta , R26
NOP
NOP
RJMP Again
$end Asm
Why not stick to this thread ? No need for a new one.
Quote:
However I'm still having issues interfacing the 8255A.
Did you connect G2A (or G2B) to ALE ? |
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Posted: Apr 12, 2012 - 03:49 PM |
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Joined: Nov 01, 2005
Posts: 6326
Location: Hilversum - the Netherlands
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How is the external memory setup in the 1287 ?
And how long are the wires from 1287 to the 8255A's ? |
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Posted: Apr 12, 2012 - 05:29 PM |
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Joined: Dec 09, 2010
Posts: 154
Location: BW, Germany
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Well I thought about a new thread because the 138 works now. However I got very weird behavior on the ALE Pin. Attached is a Screenshot from the scope
Trace1: CS(output of 74HCT138) -> goes to 8255A
Trace2: A0(Output of 74HCT537) -> goes to 8255A
Trace3: A1(Output of 74HCT537) -> goes to 8255A
Trace4: ALE(Output from 1287) -> goes to 74HCT537 and 74HCT138
This is only the initialization of the XMEM and the 8255A. I had a look at the dissassembly and found exactly what expected.
Code:
#define PIO_CTRL 0xC003
#define PIO_INIT 0x90
void xmem_init()
{
XMCRA = (1 << SRE);
XMCRB = 0x00;
uint8_t *l;
l = (uint8_t *) (PIO_CTRL);
*l = PIO_INIT;
}
I don't really understand the ALE Signal on this one.
After this initialization I am only able to read the XMEM interface. The AVR does not generate any addresses(measured at the output of the 537) when writing to the XMEM interface.(There is no CS generated by the 74HCT537 either).
The reading part works with one flaw only Bit 0-5 are valid Bit 6 and 7 always read as 0 and there is a really strange signal on those lines.(Screenshot2)
Trace1: CS (generated by 74HCT138)(Valid)
Trace2: Data on Bit0 (valid)
Trace3: Data on Bit7 invalid and strange
Note that this zoomed out really far(Still operating at 2MHz)
However I believe that this is another soldering issue or do you have any explanation for this kind of trace?
About the length of the wires: Probably about 20cm. |
Last edited by MannImMond on Apr 13, 2012 - 09:31 AM; edited 2 times in total
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Posted: Apr 12, 2012 - 05:54 PM |
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Joined: Nov 01, 2005
Posts: 6326
Location: Hilversum - the Netherlands
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When you write "137", do you mean the 74HCT138 ?
When you write "537", do you mean the 74HCT573, the octal latch ?
ALE is used to latch the lower address bits before portA is used as databus.
Have a look at your schematic: you are using ALE (PE2) also as bootloader switch input. With 10nF on that pin it will be tough for PE2 to generate ALE 
And once again: did you connect ALE to G2A (last time I ask) ? |
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Posted: Apr 12, 2012 - 06:00 PM |
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Joined: Dec 09, 2010
Posts: 154
Location: BW, Germany
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Plons wrote:
When you write "137", do you mean the 74HCT138 ?
When you write "537", do you mean the 74HCT573, the octal latch ?
Yes to both I'll correct it
Quote:
ALE is used to latch the lower address bits before portA is used as databus.
Have a look at your schematic: you are using ALE (PE2) also as bootloader switch input. With 10nF on that pin it will be tough for PE2 to generate ALE
I'll remove the corresponding R and C.
Quote:
And once again: did you connect ALE to G2A (last time I ask) ?
Yes, did that just forgot to mention it sorry. |
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Posted: Apr 12, 2012 - 06:13 PM |
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Joined: Nov 01, 2005
Posts: 6326
Location: Hilversum - the Netherlands
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Okay. Next step.
The odd looking signal looks like a line that is tri-stated (floating) It was high during the /Cs
Before looking at the data, you need to make sure that the timing for the 8255A is correct.
To check that: write a small program that writes data to the 8255A, then reads data from it; then make it pause for 100us or so. And loop.
Put the channel with the trigger of the scope on the 8255A-/CS-pin, negative edge triggered. Channel 2 on 8255A-/Rd and Channel 3 on 8255A-/Wr. What is the width of the /Rd and /Wr pulse ?
And are the /Rd and /Wr pulse low during /Cs ?
/Cs must go low first; when true /Rd or /Wr can go low but all that time /Cs must be stable and low. So /Cs comes first, leaves last.
<dinner> |
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Posted: Apr 12, 2012 - 07:16 PM |
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Joined: Dec 09, 2010
Posts: 154
Location: BW, Germany
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Plons wrote:
Okay. Next step.
The odd looking signal looks like a line that is tri-stated (floating) It was high during the /Cs
Yeah that's what I suspected but I don't see the difference to the AD0-AD5. (This behaviour occurs regardless whether the 8255A is connected or not)
Quote:
[...]
Put the channel with the trigger of the scope on the 8255A-/CS-pin, negative edge triggered. Channel 2 on 8255A-/Rd and Channel 3 on 8255A-/Wr. What is the width of the /Rd and /Wr pulse ?
And are the /Rd and /Wr pulse low during /Cs ?
/Cs must go low first; when true /Rd or /Wr can go low but all that time /Cs must be stable and low. So /Cs comes first, leaves last.
<dinner>
Will try tomorrow since I currently don't have access to the scope.
Since I don't have access to the scope I tinkered with the SW a bit. The 8255A uses the High Active Reset. However the uC seems to try to init the 8255A too quickly(because they have different Reset signals). When I use a delay of 2secs at the very beginning of the program(before initializing the 8255A) I can write to the 8255 but can't read anymore. I hope the scope will shed some light on this.
Edit: Do I need a special SRW0 and SRW1 setting? Currently I'm using the default values(0) |
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Posted: Apr 12, 2012 - 08:13 PM |
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Joined: Nov 01, 2005
Posts: 6326
Location: Hilversum - the Netherlands
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Quote:
The 8255A uses the High Active Reset.
T1 does take care of that, if ST1-B22 is going to the 8255A's Reset.
Quote:
When I use a delay of 2secs at the very beginning of the program
That should be enough 
Quote:
I can write to the 8255 but can't read anymore. I hope the scope will shed some light on this.
Yep, first we need to make sure that the timing of /Rd and /Wr are correct.
Quote:
Edit: Do I need a special SRW0 and SRW1 setting? Currently I'm using the default values(0)
I have no experience with the 1287 and the use of external memory. Will study the datasheet  |
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Posted: Apr 12, 2012 - 08:24 PM |
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Joined: Dec 09, 2010
Posts: 154
Location: BW, Germany
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Plons wrote:
Quote:
The 8255A uses the High Active Reset.
T1 does take care of that, if ST1-B22 is going to the 8255A's Reset.
Quote:
When I use a delay of 2secs at the very beginning of the program
That should be enough
Yeah just wanted to clear that up since I didn't post the shematic. I somehow assumed that the reset was quick enough to take place while the uC is still powering Up. It seems not... but I will measure the needed time aswell. |
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Posted: Apr 12, 2012 - 09:23 PM |
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Joined: Nov 01, 2005
Posts: 6326
Location: Hilversum - the Netherlands
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Quote:
Yeah that's why I put him there
But you do have indeed an issue with the Reset for the 8255A.
When the AVR is still in reset-mode, the 8255A is already out of it (when voltage on NRES rises above 0.8V, the Reset for the 8255A goes low). And since the AVR-pins are configured as inputs, that may cause all kins of oddities.
To fix that: you could tweak the circuit around T1, but better is to use an I/O-pin for that. Old technology mix with today's technology requires that. Use a pull-up of 4k7 and make the pin low when YOU (in SW) think it's time for the 8255A to come out of reset-mode.
Quote:
Do I need a special SRW0 and SRW1 setting? Currently I'm using the default values(0)
No, with 2MHz I/O-clock you're fine. But if you need more speed for the AVR and use f.i. a 4MHz max 5MHz crystal (CKDIV8 Fuse not set), SRWn1 = 0 and SRWn0 = 1 is needed to meet the 8255A timing requirements.
Nard |
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Posted: Apr 13, 2012 - 12:44 AM |
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Joined: Nov 01, 2005
Posts: 6326
Location: Hilversum - the Netherlands
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Btw, you *could* ditch the 74HCT573 alltogether: Connect A10 of the AVR to A0 of the 8255A's and A11 of the AVR to A1 of the 8255A's.
You'll find the first register of the first 8255A (the one on /Y3 of the 138) at:
address 0xB000 through 0xB3FF, the second register of that 8255A at address 0xB400 through 0xB7FF, etc.
This an old trick that many of the old farts here will know
And: having studied the External Memory interface of the 1287 and relatives: another feather on the head of the designers A and V for their splendid work |
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Posted: Apr 13, 2012 - 09:36 AM |
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Joined: Dec 09, 2010
Posts: 154
Location: BW, Germany
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Plons wrote:
Quote:
Yeah that's why I put him there
You're right, the name ST1-B22 gave it away
But you do have indeed an issue with the Reset for the 8255A.
When the AVR is still in reset-mode, the 8255A is already out of it (when voltage on NRES rises above 0.8V, the Reset for the 8255A goes low). And since the AVR-pins are configured as inputs, that may cause all kins of oddities.
To fix that: you could tweak the circuit around T1, but better is to use an I/O-pin for that. Old technology mix with today's technology requires that. Use a pull-up of 4k7 and make the pin low when YOU (in SW) think it's time for the 8255A to come out of reset-mode.
What kind of tweak did you have in mind? Sacrificing an IO is next to impossible since I'm already lacking about 10 I/Os
Quote:
Quote:
Do I need a special SRW0 and SRW1 setting? Currently I'm using the default values(0)
No, with 2MHz I/O-clock you're fine. But if you need more speed for the AVR and use f.i. a 4MHz max 5MHz crystal (CKDIV8 Fuse not set), SRWn1 = 0 and SRWn0 = 1 is needed to meet the 8255A timing requirements.
Nard
Well since the 16MHz Quarz is fixed(working with USB) I'm working on 2MHz(with CKDIV8) which is sufficient for the tasks but thanks for the advice anyway.
Ditching the 537 might be an idea but I'm not sure about it yet because the A10 is used in combination with another Board. |
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