View topic - SREG flag detail

Search

SREG flag detail

AVR Freaks Forum Index » AVR (8-bit) Technical Forums » AVR forum

Author

Message

alexi

Posted: Feb 14, 2006 - 08:25 PM

Joined: Jan 08, 2005
Posts: 78

Hi
i want to know more detail and descreptions about all flags in SREG how can i find it? Rolling Eyes

thanks
Alexi

sutton

Posted: Feb 14, 2006 - 08:34 PM

Joined: Oct 30, 2001
Posts: 1563
Location: Manchester England

Alexi
Look in a device manual and also a copy of the asm manual.
Most of the SREG flags are related to ALU activities. The exceptions that spring to mind are the T bit and the Global interrupt enable bit.

_________________
Keep it simple it will not bite as hard

abcminiuser

Posted: Feb 14, 2006 - 08:36 PM

Joined: Jan 23, 2004
Posts: 9832
Location: Trondheim, Norway

In your AVR's datasheet. You can download the datasheets from the Atmel website, at www.atmel.com. This will explain all the avaliable peripherals and registers for your AVR chip type.

- Dean Twisted Evil

_________________
Atmel Studio 6.1 is now released, grab it here.
Report AS6/ASF bugs here.

theusch

Posted: Feb 14, 2006 - 08:52 PM

Joined: Feb 19, 2001
Posts: 25923
Location: Wisconsin USA

Quote:

...also a copy of the asm manual...

Righto. The datasheet won't give you any detail. Let's hunt up the doc for OP...
http://www.atmel.com/dyn/resources/prod ... oc0856.pdf

Lee

alexi

Posted: Feb 15, 2006 - 06:10 AM

Joined: Jan 08, 2005
Posts: 78

theusch wrote:

Quote:

...also a copy of the asm manual...

Righto. The datasheet won't give you any detail. Let's hunt up the doc for OP...
http://www.atmel.com/dyn/resources/prod ... oc0856.pdf

Lee

i read it before, it's Instruction set with mixing SREG flags(not bad), but i want more about SREG flags duty.
Crying or Very sad

Alexi

sutton

Posted: Feb 15, 2006 - 11:30 AM

Joined: Oct 30, 2001
Posts: 1563
Location: Manchester England

Fail to understand the question

Quote:

but i want more about SREG flags duty.

Suspect you need to read up on Binary arithmatic and the 8 bit micro!

_________________
Keep it simple it will not bite as hard

clawson

Posted: Feb 15, 2006 - 11:47 AM

Joined: Jul 18, 2005
Posts: 62354
Location: (using avr-gcc in) Finchingfield, Essex, England

Alexi,

Well, simplistically, 6 of the flags (C, V, N, S, H, Z) are set my most arithmetic/logical operators (each op says which bits it might set/clear and in what circumstances) and then, on the whole, they are used for various conditional branch opcodes (though that's a GROSS generalisation!). So you might SUBI a large number from a small number resulting in (amongst other things) the C(arry) flag being set and then use this in a BRCS instruction. But there are other uses such as a 16 bit rotate where you might LSL a lower half register (and top bit goes into C bit in SREG) and then ROL the upper register both to shift its bits to the left and brings the C bit into the lowest bit position.

The T bit is just a "handy place" to store a bit flag setting and access using BST and BLD

And the I flag is the global interrupt control for the CPU (set/cleared with SEI and CLI). When it is 0 the AVR cannot be interrupted.

As sutton says you either need to read up on this stuff if you are planning to write assembler or stick with C in which case all this goes on "behind the scenes" and you only need to worry about it when debugging mixed C/assembly (which is a good way to learn assembler I think!)

Cliff

_________________

alexi

Posted: Feb 15, 2006 - 09:04 PM

Joined: Jan 08, 2005
Posts: 78

thanks Cliff for your guide,actually i want to define fraction binary number in my assembly language,(i.e 0.46875),so i did 1*(2e-2 + 2e-3 + 2e-4 + 2e-5)=0.46875 please look code:

Code:

1)ldi   r16,1

2)ror   r16

3)ror   r16      ;*2e-2

4)mov   r17,r16

5)ror   r16

6)add   r17,r16

7)ror   r16

8)add   r17,r16

9)ror   r16

10)add   r17,r16

my question is:
1-after line 2 S and V flags set,why?
2-after line 3 S cleared and V and N flags set,why?

thanks
Alexi

theusch

Posted: Feb 15, 2006 - 09:32 PM

Joined: Feb 19, 2001
Posts: 25923
Location: Wisconsin USA

??? If you know what binary value you want in the register(s) at the end of the sequence, why don't you just use 1 word and 1 cycle and load the binary pattern with a single LDI?

Yes, the manual just says that in SREG, C is the Carry Flag. It summarizes which comparison instructions set which SREG flags. In the discussion of each instruction, it gives a table of which flags are affected.

If you don't understand the concept of C and Z flags as a result of processor operations, then it is certainly true that this document is not for you.

Lee

MartinM57

Posted: Feb 15, 2006 - 11:24 PM

Joined: Dec 15, 2005
Posts: 826
Location: Bristol, UK

alexi wrote:

...

Code:

1)ldi   r16,1

2)ror   r16

3)ror   r16      ;*2e-2

4)...

my question is:
1-after line 2 S and V flags set,why?
2-after line 3 S cleared and V and N flags set,why?

thanks
Alexi

I think those are good questions. Maybe a bit academic, since it doesn't really matter why they are set in this code, though.

For ROR the manual says
S = N exclusive or V (if I read the cross in a circle symbol correctly)

...and neither N or V are is defined very well elsewhere in the manual.

I do see that BRGE tests the S (Signed Flag) and the simple example
cp r11, r12
brge greateq
is probably all you ever need to really need to know. But understanding why it S is set when you "ror 1" isn't a bad question in my view....

JohanEkdahl

Posted: Feb 15, 2006 - 11:44 PM

Joined: Mar 27, 2002
Posts: 18586
Location: Lund, Sweden

From the first page of the document "AVR Instruction Set":

Quote:

N: Negative Flag
V: Two’s complement overflow indicator

I share Martins

Quote:

understanding why it S is set when you "ror 1" isn't a bad question

(or I'm just too tired to see how You use this)

Or is it just an "artefact"? Come on Lee, the well of immense knowledge - enlighten us!

MartinM57

Posted: Feb 16, 2006 - 12:23 AM

Joined: Dec 15, 2005
Posts: 826
Location: Bristol, UK

JohanEkdahl wrote:

From the first page of the document "AVR Instruction Set":

Quote:

N: Negative Flag
V: Two’s complement overflow indicator

Yeh, as I said, not well explained!

N == bit 7 set?
V == ???

Koshchi

Posted: Feb 16, 2006 - 01:05 AM

Joined: Nov 17, 2004
Posts: 13851
Location: Vancouver, BC

The V flag is set when the Carry flag and the Negative flag are not equal. Since, in the case of ROR, the N flag (bit7) contains the previous value of the C flag, it indicates that the C flag has changed.

The S flag is set when the V flag and the N flag are not equal. But since the N flag is the previous C flag and the V flag indicates whether the C flag has changed, it effectively gives you the current C flag, so it is not that useful in ROR.

When shifting in the other direction it is more useful since it indicates whether the N flag has changed, which is important when you are working with signed numbers.

Edit: For ROL, the V flag indicates that the N flag has changed. The S flag holds the opposite of the N flag if V is set, and the same as the N flag if V is not set. Still, this is for use with signed numbers.

As far as your code is concerned, I don't think that it is doing what you think it is. If you intend that bit7 represents 0.5, then you need one more ROR after the LDI since the first ROR only moves the bit into the Carry flag. The second one moves it into bit7. I think that it would make more sense to put the bit in the proper position to start with, like this:

Code:

ldi r16, 0b10000000 ;start with 2e-1

ror r16 ;2e-2

mov r17, r16

...

_________________
Regards,
Steve A.

The Board helps those that help themselves.

Last edited by Koshchi on Feb 16, 2006 - 01:21 AM; edited 1 time in total

Koshchi

Posted: Feb 16, 2006 - 01:11 AM

Joined: Nov 17, 2004
Posts: 13851
Location: Vancouver, BC

Quote:

N == bit 7 set?

Yes.

Quote:

V == ???

How V is calculated and its precise meaning depends greatly on what operation you are doing. You have to look at the individual commands.

_________________
Regards,
Steve A.

The Board helps those that help themselves.

MartinM57

Posted: Feb 16, 2006 - 08:21 AM

Joined: Dec 15, 2005
Posts: 826
Location: Bristol, UK

Aha - the trick I missed is to not RTFM carefully enough, but that explanation helps a lot too! Thanks

Still of the view that it's a good question though.... Smile

wagnerlip

Posted: Feb 10, 2012 - 04:24 AM

Joined: Nov 05, 2006
Posts: 37
Location: Orlando Florida USA

Complementing Koschi, 5 years later...

The "signed" operation and flags is only in the mind of the programmer, since the machine doesn't know the bits in the register represent a signed value or not.

So, by using tricky logic in the ALU, the flags can give hints to the programmer about what could be possibly correct for operations results, in case the programmer is thinking in signed values.

N FLAG

Whenever a register has the bit 7 "on", it simply could represent value 128d, or, if the programmer is considering signed values, a negative value of bits 0-6.

Without knowing much, the ALU will always set flag N=1 when bit 7 is "on", it doesn't know better.

So, if the programmer is considering "signed values", he could look at the bit 7 of the register just exercised by the ALU, or, just look at the N flag. If bit 7 or N Flag is "on", then the "contents" in the register considering to be signed, is negative.

The flags has different logic for different instructions.

ADD and ADC uses LOGIC "A" below.

SUB, CP, CPI and SUBI uses LOGIC "B" below.

=============
Just a reference for signed numbers:

0x7F = + 127 (the more positive for signed 8 bits)
0x7E = + 126
...
0x03 = + 3
0x02 = + 2
0x01 = + 1
0x00 = 0
0xFF = - 1
0xFE = - 2
0xFD = - 3
...
0x87 = - 121
0x86 = - 122
0x85 = - 123
0x84 = - 124
0x83 = - 125
0x82 = - 126
0x81 = - 127
0x80 = - 128 (the more negative for signed 8 bits)

LOGIC A: ADDITIONS

For V flag: If both registers have 7 bit "on", the result (of the addition) has bit 7 (N flag) "off" and C flag is also "on", you could see an AND gate with four inputs for V = N&N&/N&C.

In this case, V flag means the result is negative and larger than -128, larger than could fit in 7 bits for possible signed values. You can think as a special Carry bit for signed values.

When adding 0x83 + 0x83 (-125 + -125) the result should be -250, but the signed values in 8 bits could hold up to 0x80 = -128, so V flag is turned on and the result is 0x06.

Code:

   Ldi R20,0x83   ; N=1

   Ldi R21,0x83   ; N=1

   Add R20,R21

Result R20 = 0x06 V=1 N=0 S=1 C=1

Logic: V=N&N&/N&C
Logic: V=1&1&/0&C = 1

In this situation the programmer has two options:

a) convert the result to 16 bits, adding 0xFF as the most significant byte: 0xFF06, means decimal -250.

b) keep the 0x06 for that byte and take this "negative carry" in consideration in a multi-byte addition.

Simply put, in additions, V flag will never turn on if one register has bit 7 "off" (positive value if thinking signed operation).

For N flag: The N flag of the result after the addition.

For S flag: The exclusive or between N and V

LOGIC B : SUBTRACTIONS AND COMPARISONS

SUB R20,R21

For V flag: If R20 has bit 7 "on" (N=1), R21 has bit 7 "off" (N=0), the result has bit 7 "off" (N=0) then V=1. Here a three inputs AND. V = N & /N & /N.

For N flag: Just the bit 7 of R20 after the subtraction.

Again, the S flag goes "on" if the exclusive-or between N and V results "on".

So, with N flag "on" and V flag "off", they met the 'exclusive or' condition to set S flag. So, S flag goes "on", telling the programmer the result's value is from 0x80-0xFF, is negative and valid.

Now consider this:

Code:

   Ldi  R20,0x82

   Ldi  R21,0x05

   Sub  R20,R21

Result is R20 = 0x7D S=1 V=1 N=0
Oooowwa !!!

0x7D is a positive number, signed or not.
How come -126 - +5 = +125 ???
It is wrong, isn't it?

But now, the ALU may alert the programmer about it in a simply tricky logic way. Check flags.

Before the subtraction, R20 bit 7 = "on" (N=1), R21 bit 7 = "off" (N=0), result bit 7 = "off" (N=0), this satisfy the logic above for V flag becomes "on".

Also, the N=0 and V=1 of the results makes the exclusive-or for S flag becomes "on".

This tells the programmer that the signed flag is ON, but the V flag "on" tells him the result doesn't fit into 7 bits, because -126 - +5 = -131, the biggest negative number in 8 bits is 0x80 (-128).

Upon those flags, the programmer has two ways:

a) He could simple ignore the result and force a inverse operation, ADD instead of SUB, so 0x82 + 0x05 = 0x87. In this case, N bit is "on", V bit is "off", S bit is "on", meaning, 0x82 is a negative and correct number.

b) He could inverse operation twice over the result.
0x7D + 0x05 + 0x05 = 0x87, what is the correct result, N=1 V=0 S=1.

Code:

   Ldi  R20,0x82

   Ldi  R21,0x05

   Sub  R20,R21

   Brge PC+4      ; S=0 ?

   Brvc PC+3      ; V=0 ?

   Add  R20,R21

   Add  R20,R21

   ...

There is a way to avoid it. Before the subtraction, just make a comparison between both operands, CP R20,R21. The flags will behave exactly the same as for the subtraction, without altering R20. So you can anticipate the flags.

Code:

   Ldi  R20,0x82

   Ldi  R21,0x05

   Cp   R20,R21

   ...

Result is R20 = 0x82 S=1 V=1 N=0

Now, upon S=1 and V=1, just don't do the SUB and do an ADD instead.

Code:

Add R20,R21

Result is R20 = 0x87 S=1 V=0 N=1
The flags say the number is signed, negative and correct.

Code:

   Ldi  R20,0x82

   Ldi  R21,0x05

   Cp   R20,R21

   Brge PC+4      ; S=0 ?

   Brvc PC+3      ; V=0 ?

   Add  R20,R21

   Rjmp PC+1

   Sub  R20,R21

   ...

Hey, but this code is one instruction longer than the one above that first subtract than check and correct with two additions if necessary.

For ROL, ROR, ASR, LSL, LSR

Consider any LEFT movement a simply ADD instruction.
In fact, LSL instruction opcode is exactly the same as adding the register to itself.

Code:

   LSL R18

   ADD R18,R18

both have exactly the same instruction in binary, 0x0F22

For the Right shifts, it depends on the previous bit positions and values. Always think about how you would do a shift or rotation using ADD or SUBTRACT, and the behavior of the flags will be the same.

For example,

Code:

   Ldi R20,0x80

   LSL R20

results in R20 = 0, S=1 V=1 Z=1 C=1

It is exactly the same as doing

Code:

   Ldi R20,0x80

   Add R20,R20

Because even the instruction is the same as LSL

Now, when doing ROR, you are including the Carry flag into bit 7 of the register.

Code:

   Ldi R20,0x40

   SEC

   Ror R20

   ; is the same as

   Ldi R20,0x40

   Lsr R20

   Add R20,0x80

Results R20 = 0xC0 V=1 N=1

In the question posted by Alexi, years ago:

Code:

1)ldi   r16,1 

2)ror   r16

If Carry flag was zero at the start,
Results R16 = 0 C=1 S=1 V=1
His question was about why S and V = 1.

I am going to explain it using another example

Code:

    Ldi R20,11010000b  ; 0xD0

    Lsl R20            ; 0xA0 = 10100000b C=1 S=1 N=1 

    Lsl R20            ; 0x40 = 01000000b C=1 S=1 V=1 

    Lsl R20            ; 0x80 = 10000000b V=1 N=1

    Lsl R20            ; 0x00 = 00000000b C=1 S=1 V=1 Z=1

Observe that whenever bit 7 is "on", N flag MUST BE also "on". Also, whenever bit 7 is "on" and drops into Carry Flag on the LSL instruction, it means larger than a possible signed number, or it is larger than -128 or smaller than 1, in any way the ALU must signal the programmer that a possible signed operation goes awry, went south (lower than Florida where I live). This is exactly the same as ROR 0x01 or LSR 0x01, the hot bit goes into Carry flag and it requires programmer special intervention when dealing with signed operation, since just the Carry flag is not enough.

There is also the particular issue of S flag being "N exclusive-or V", it is a rule that you can not forget.

Interesting enough, V flag is an "exclusive-or" between N flag and C flag. It follows that rule of:
VLogic: V=N1&N2&/N3&C
Logic: V=1&1&/0&C = 1

Where:
N1, N2 and C is Bit7 previous of LSL, Actual Carry flag.
N3 is Bit7 after LSL, Actual Bit7 or N flag.

The only way to not lift V flag is when N3 is "on" with Carry flag. At first, it seems to be a failure of the logic, since it "thinks" that having N flag "on", bit7=1, the S flag is on, indicating valid negative number, but the overflow happened (C flag), it should turn on V flag, but then again, the main rule doesn't allow it to show V flag, since S = N xor V, and the three can NOT happen at the same time.

This also happen when Adding $D0 and $D0, flags S N C are "on", result is 0xA0. Without the V flag you will not be able to propagate the "negative carry" in a multi-byte addition. You must then use the C flag to do the job.

The answer? it is smart. It knows it was an addition, or a left shift/rotate, the carry will be enough.

It also explains Alexi's question, when shifting RIGHT: Shift Right is considered a subtraction for the rule, then, instead of N being set along with S, V takes over, indicating a half-bit in C flag.

Smart. Really smart. Atmel developers are very good. I would love to see the V flag gate logic representation tied to the ALU. It should be amazing.

I wonder in what kind of trickery we could use those functions for other purposes.

Wagner Lipnharski
Orlando Florida.