| Author |
Message |
|
|
 Posted: Mar 19, 2011 - 06:17 PM |
|
Joined: Mar 19, 2011
Posts: 6
|
|
Hey all, new user here (first post).
This device may be too new, but I'm wondering if anyone knows why Atmel is using a SMC chip select for SDRAM as opposed to the dedicated SDRAM Chip Select on the AT32UC3C eval board? I can understand the "sharing" of pin functions for flexibility (SDRAM SDCS and SMC NCS[1] are shared), but if the dedicated SDRAM Chip Select is not being used (they are using it to drive a generic LED, which could have easily been some other GPIO) why on Earth would you use a shared SMC Chip Select instead of the dedicated SDRAM Chip Select?
I tend to use signals as they are intended (for example SDCS for SDRAM Chip Select) so as to avoid confusion, but I'm somewhat hesitant to do so since the eval board uses the SMC NCS[1] for SDRAM chip select instead of SDCS.
Any experience with this out there? (and yes I have sent an email to Atmel)
This has also been by far THE worst written datasheet I have ever seen...and I'm not even dealing with the firmware, only hardware!
Bill |
|
|
| |
|
|
|
|
|
|
Posted: Mar 20, 2011 - 08:45 PM |
|
Joined: Jan 07, 2003
Posts: 4580
Location: Oslo, Norway
|
|
You should use SDCS, not NCS[1]. Trust the datasheet 
Also, if you think the datasheet is bad, let Atmel know, then they can fix it.
PS! You also have the schematic checklist appnote for UC3C; AVR32768. |
|
|
| |
|
|
|
|
|
|
Posted: Mar 21, 2011 - 01:41 AM |
|
Joined: Mar 19, 2011
Posts: 6
|
|
NCS[1] IS valid for SDRAM chip select according to the datasheet, and is shown as such in an application schematic, yet SDCS is shown in the SDRAM controller block diagram. On top of that the eval board uses NCS[1] for SDRAM. I just don't know if there is any difference between using one or the other.
I fully intend to let Atmel know of the problems with this datasheet (in a professional manner of course ).
I will dig through whatever extra documentation is available. |
|
|
| |
|
|
|
|
|
|
Posted: Mar 23, 2011 - 02:05 AM |
|
Joined: Mar 19, 2011
Posts: 6
|
|
No other helpful documentation found, including that "schematic checklist"...and still no answer from Atmel.
Quite disappointing indeed... |
|
|
| |
|
|
|
|
|
|
Posted: Mar 24, 2011 - 01:24 PM |
|
Joined: Mar 19, 2011
Posts: 6
|
|
From Atmel (finallY):
The EBI-SDCS (SDRAMC Chip Select, PC13) should be ignored as it is
the datasheet mistake.
This signal will be removed from the datasheet in future revisions.
So you can use EBI-NCS[1] pin only. |
|
|
| |
|
|
|
|
|
|
Posted: Mar 24, 2011 - 01:32 PM |
|
Joined: Oct 10, 2007
Posts: 395
Location: Valls, Spain
|
|
Well the UC3C documentation is definitely a piece of ...
I can see why many people is complaining about it! |
_________________
Daniel Campora
http://www.lear.com
|
| |
|
|
|
|
|
|
Posted: Jan 31, 2012 - 06:00 PM |
|
Joined: Jan 31, 2012
Posts: 1
|
|
Hi,
I am using AT32UC3A0512 on my board and using NCS[1] as chip select for SDRAM. What I observe is thechip select is continuously low (even after enabling intenal pull up). Has anybody observed this behavior (is it normal)? |
|
|
| |
|
|
|
|
|
FAQ
Search
Register
Log in to check your private messages
Log in
Maximize
RSS
