AVRFreaks.net

#include <avr/io.h>
#include <avr/pgmspace.h>
#include <util/delay.h>
#include "SSD1305.h"

#define SSD1305_DATA_PORT      PORTH_OUT
#define SSD1305_DATA_DIR      PORTH_DIR
#define SSD1305_DATA_PIN      PORTH_IN

#define SSD1305_CONTROL_PORT   PORTJ_OUT
#define SSD1305_CONTROL_DIR      PORTJ_DIR

#define SSD1305_RD            (1 << PIN0)   //Read
#define SSD1305_WR            (1 << PIN1)   //Write
#define SSD1305_DC            (1 << PIN2)   //Data Or Command
#define SSD1305_RES            (1 << PIN3)   //Reset
#define SSD1305_CS            (1 << PIN4)   //Chip select

void GLCD_WriteData(unsigned char dataToWrite)
{
SSD1305_CONTROL_PORT |= (SSD1305_RD | SSD1305_DC);
SSD1305_CONTROL_PORT &= ~(SSD1305_CS |SSD1305_WR);
SSD1305_DATA_PORT = dataToWrite;
asm("nop");
SSD1305_CONTROL_PORT |= (SSD1305_WR);
}

void GLCD_WriteCommand(unsigned char commandToWrite)
{
SSD1305_CONTROL_PORT |= (SSD1305_RD);
SSD1305_CONTROL_PORT &= ~(SSD1305_CS |SSD1305_WR | SSD1305_DC);
SSD1305_DATA_PORT = commandToWrite;
asm("nop");
SSD1305_CONTROL_PORT |= (SSD1305_WR);
}

void GLCD_InitializePorts(void)
{   
SSD1305_CONTROL_DIR |= (SSD1305_DC | SSD1305_WR | SSD1305_RD | SSD1305_CS | SSD1305_RES);  //setta direzione 1 output
SSD1305_DATA_DIR = 0xFF;   //setta direzione 1 output
SSD1305_CONTROL_PORT &= ~ (SSD1305_DC | SSD1305_WR | SSD1305_RD | SSD1305_CS | SSD1305_RES); //setta i pin a 0
SSD1305_CONTROL_PORT |= (SSD1305_RES);  //Reset  High
_delay_ms(1);
SSD1305_CONTROL_PORT &= ~ (SSD1305_RES);  //Reset  Low
_delay_ms(10);
SSD1305_CONTROL_PORT |= (SSD1305_RES);  //Reset  High runtime mode
_delay_ms(1);
}

unsigned char GLCD_ReadData(void)
{
unsigned char tmp;
SSD1305_CONTROL_PORT |= (SSD1305_DC | SSD1305_WR);
SSD1305_CONTROL_PORT &= ~(SSD1305_CS | SSD1305_RD);
asm("nop");
SSD1305_DATA_DIR = 0x00;
asm("nop");
tmp =  SSD1305_DATA_PIN;
SSD1305_CONTROL_PORT |= (SSD1305_RD);
return tmp;
}

unsigned char GLCD_ReadByteFromROMMemory(unsigned char * ptr)
{
return pgm_read_byte(ptr);
}

void GLCD_Initialize(void)
{
GLCD_InitializePorts();
GLCD_WriteCommand(SSD1305_DISPLAYOFF);  // 0xAE
GLCD_WriteCommand(SSD1305_SETDISPLAYCLOCKDIV);  // 0xD5
GLCD_WriteCommand(0x80);  // the suggested ratio 0x80
GLCD_WriteCommand(SSD1305_SETMULTIPLEX); // 0xA8
GLCD_WriteCommand(0x3F);  // 0x3F 1/64 duty
GLCD_WriteCommand(SSD1305_SETDISPLAYOFFSET); // 0xD3
GLCD_WriteCommand(0x0); // no offset
GLCD_WriteCommand(SSD1305_SETSTARTLINE); // line #0
//GLCD_WriteCommand(SSD1305_SEGREMAP1); //0xA1
GLCD_WriteCommand(SSD1305_COMSCANDEC); //0xC8
GLCD_WriteCommand(SSD1305_SETCOMPINS); // 0xDA
GLCD_WriteCommand(0x12); // disable COM left/right remap
GLCD_WriteCommand(SSD1305_SETCONTRAST);
GLCD_WriteCommand(0xFF);
GLCD_WriteCommand(SSD1305_SETPRECHARGE); // 0xd9
GLCD_WriteCommand(0xF1);
GLCD_WriteCommand(SSD1305_SETVCOMDETECT); // 0xDB
GLCD_WriteCommand(0x40); // 0x20 is default?
GLCD_WriteCommand(SSD1305_DISPLAYALLON_RESUME); // 0xA4
GLCD_WriteCommand(SSD1305_NORMALDISPLAY); // 0xA6
GLCD_WriteCommand(SSD1305_MEMORYMODE); // 0x20
GLCD_WriteCommand(0x00); // 0x0 act like ks0108
GLCD_WriteCommand(SSD1305_SETLOWCOLUMN | 0x0);  // low col = 0
GLCD_WriteCommand(SSD1305_SETHIGHCOLUMN | 0x0);  // hi col = 0
//GLCD_WriteCommand(SSD1305_SEGREMAP | 0x1);
GLCD_WriteCommand(SSD1305_DISPLAYON);//--turn on oled panel
}

unsigned char GLCD_ReadData(void)
{
unsigned char tmp;
SSD1305_DATA_DIR = 0x00;
SSD1305_CONTROL_PORT &= ~(SSD1305_CS);
SSD1305_CONTROL_PORT |= (SSD1305_DC | SSD1305_WR);
SSD1305_CONTROL_PORT &= ~(SSD1305_RD);
SSD1305_CONTROL_PORT |= (SSD1305_RD);
SSD1305_CONTROL_PORT &= ~(SSD1305_RD);
SSD1305_CONTROL_PORT |= (SSD1305_RD);
SSD1305_CONTROL_PORT |= (SSD1305_CS);
tmp =  SSD1305_DATA_PIN;
SSD1305_DATA_DIR = 0xFF;
return tmp;
}